ATAM862P-TNSY4D Atmel, ATAM862P-TNSY4D Datasheet - Page 43

• Manufacturer Part Number: ATAM862P-TNSY4D
• Description: IC MCU FLASH 4K TX 433MHZ 24SSOP
• Manufacturer: Atmel

Specifications of ATAM862P-TNSY4D

• Applications: UHF ASK/FSK
• Core Processor: MARC4
• Program Memory Type: FLASH (4 kB)
• Controller Series: MARC4 4-Bit
• Ram Size: 256 x 4
• Interface: SSI
• Number Of I /o: 11
• Voltage - Supply: 1.8 V ~ 4 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 24-SSOP
• Processor Series: ATAM862x
• Core: MARC4
• Data Bus Width: 4 bit
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

22.7
4551G–4BMCU–07/07
Timer 1
Figure 22-6. UTCM Block Diagram
The Timer 1 is an interval timer which can be used to generate periodical interrupts and as pres-
caler for Timer 2, Timer 3, the serial interface and the watchdog function.
The Timer 1 consists of a programmable 14-stage divider that is driven by either SUBCL or
SYSCL. The timer output signal can be used as prescaler clock or as SUBCL and as source for
the Timer 1 interrupt. Because of other system requirements, the Timer 1 output T1OUT is syn-
chronized with SYSCL. Therefore, in the power-down mode SLEEP (CPU core -> sleep and
OSC-Stop -> yes), the output T1OUT is stopped (T1OUT = 0). Nevertheless, the Timer 1 can be
active in SLEEP and generate Timer 1 interrupts. The interrupt is maskable via the T1IM bit and
the SUBCL can be bypassed via the T1BP bit of the T1C2 register. The time interval for the
timer output can be programmed via the Timer 1 control register T1C1.
T3I
T2I
SYSCL
SUBCL
T1OUT
TOG3
POUT
TOG2
from clock module
MUX
MUX
MUX DCG
MUX
MUX
8-bit Counter 3
8-bit shift register
Compare 3/1
Compare 3/2
4-bit Counter 2/1
Transmit buffer
Receive buffer
Capture 3
Compare 2/1
8-bit Counter 2/2
Interval / Prescaler
Timer 1
Timer 3
Timer 2
Compare 2/2
Control
SSI
Watchdog
Control
Demodu-
Control
Modu-
Modu-
lator 3
lator 3
lator 2
SCL
I/O bus
ATAM862-4
NRST
INT2
INT5
INT4
INT3
T3O
T2O
SC
SD
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