ATAM862P-TNSY4D Atmel, ATAM862P-TNSY4D Datasheet - Page 58

IC MCU FLASH 4K TX 433MHZ 24SSOP

ATAM862P-TNSY4D

Manufacturer Part Number
ATAM862P-TNSY4D
Description
IC MCU FLASH 4K TX 433MHZ 24SSOP
Manufacturer
Atmel
Datasheet

Specifications of ATAM862P-TNSY4D

Applications
UHF ASK/FSK
Core Processor
MARC4
Program Memory Type
FLASH (4 kB)
Controller Series
MARC4 4-Bit
Ram Size
256 x 4
Interface
SSI
Number Of I /o
11
Voltage - Supply
1.8 V ~ 4 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
24-SSOP
Processor Series
ATAM862x
Core
MARC4
Data Bus Width
4 bit
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
23. Timer 3
23.1
Figure 23-1. Timer 3
58
Features
ATAM862-4
CL3
Compare register 1
Compare register 2
8-bit comparator
Capture register
8-bit counter
Timer 3 consists of an 8-bit up-counter with two compare registers and one capture register. The
timer can be used as event counter, timer and signal generator. Its output can be programmed
as modulator and demodulator for the serial interface. The two compare registers enable various
modes of signal generation, modulation and demodulation. The counter can be driven by inter-
nal and external clock sources. For external clock sources, it has a programmable
edge-sensitive input which can be used as counter input, capture signal input or trigger input.
This timer input is synchronized with SYSCL. Therefore, in the power-down mode SLEEP (CPU
core -> sleep and OSC-Stop -> yes), this timer input is stopped too. The counter is readable via
its capture register while it is running. In capture mode, the counter value can be captured by a
programmable capture event from the Timer 3 input or Timer 2 output.
Two Compare Registers
Capture Register
Edge Sensitive Input with Zero Cross Detection Capability
Trigger and Single Action Modes
Output Control Modes
Automatically Modulation and Demodulation Modes
FSK Modulation
Pulse Width Modulation (PWM)
Manchester Demodulation Together with SSI
Biphase Demodulation Together with SSI
Pulse-width Demodulation Together with SSI
TOG2
RES
Control
Control
T3I
C32
C31
NQ
NQ
D
D
T3SM2
T3SM1
CM31
CM32
T3RM1
T3RM2
T3EIM
T3IM1
T3IM2
T3TM1
T3TM2
: T3M1
: T3M2
4551G–4BMCU–07/07
INT5
TOG3

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