ATAM862P-TNSY4D Atmel, ATAM862P-TNSY4D Datasheet - Page 44

• Manufacturer Part Number: ATAM862P-TNSY4D
• Description: IC MCU FLASH 4K TX 433MHZ 24SSOP
• Manufacturer: Atmel

Specifications of ATAM862P-TNSY4D

• Applications: UHF ASK/FSK
• Core Processor: MARC4
• Program Memory Type: FLASH (4 kB)
• Controller Series: MARC4 4-Bit
• Ram Size: 256 x 4
• Interface: SSI
• Number Of I /o: 11
• Voltage - Supply: 1.8 V ~ 4 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 24-SSOP
• Processor Series: ATAM862x
• Core: MARC4
• Data Bus Width: 4 bit
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 22-8. Timer 1 and Watchdog
44
ATAM862-4
CL1
T1C1 register
Write of the
T1C1
WDC
T1RM T1C2 T1C1 T1C0
WDL
This timer starts running automatically after any power-on reset! If the watchdog function is not
activated, the timer can be restarted by writing into the T1C1 register with T1RM = 1.
Timer 1 can also be used as a watchdog timer to prevent a system from stalling. The watchdog
timer is a 3-bit counter that is supplied by a separate output of Timer 1. It generates a system
reset when the 3-bit counter overflows. To avoid this, the 3-bit counter must be reset before it
overflows. The application software has to accomplish this by reading the CWD register.
After power-on reset the watchdog must be activated by software in the $RESET initialization
routine. There are two watchdog modes, in one mode the watchdog can be switched on and off
by software, in the other mode the watchdog is active and locked. This mode can only be
stopped by carrying out a system reset.
The watchdog timer operation mode and the time interval for the watchdog reset can be pro-
grammed via the watchdog control register (WDC).
Figure 22-7. Timer 1 Module
WDR WDT1 WDT0
Decoder
Decoder
3
RES
CL
2
SUBCL
SYSCL
Q1 Q2 Q3 Q4
mode control
Watchdog
MUX
RES
T1CS
Q5
MUX for watchdog timer
MUX for interval timer
Q6
CL1
Q8
Q8
Prescaler
14 bit
Q11
Q11
T1MUX
WDCL
Q14
Q14
T1BP
T1C2
T1MUX
SUBCL
WDCL
T1BP T1IM
T1IM
Divider / 8
Watchdog
Watchdog
4 bit
Divider
RESET
CWD register
T1IM=0
T1IM=1
Read of the
NRST
INT2
T1OUT
INT2
T1OUT
RESET
(NRST)
4551G–4BMCU–07/07