ATAM862P-TNSY4D Atmel, ATAM862P-TNSY4D Datasheet - Page 69

• Manufacturer Part Number: ATAM862P-TNSY4D
• Description: IC MCU FLASH 4K TX 433MHZ 24SSOP
• Manufacturer: Atmel

Specifications of ATAM862P-TNSY4D

• Applications: UHF ASK/FSK
• Core Processor: MARC4
• Program Memory Type: FLASH (4 kB)
• Controller Series: MARC4 4-Bit
• Ram Size: 256 x 4
• Interface: SSI
• Number Of I /o: 11
• Voltage - Supply: 1.8 V ~ 4 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 24-SSOP
• Processor Series: ATAM862x
• Core: MARC4
• Data Bus Width: 4 bit
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

23.6.4
23.6.5
4551G–4BMCU–07/07
Timer 3 Clock Select Register (T3CS)
Timer 3 Compare- and Compare-mode Register
Table 23-2.
Table 23-3.
Timer 3 has two separate compare registers T3CO1 and T3CO2 for the 8-bit stage of Timer 3.
The timer compares the content of the compare register with the current counter value. If both
match, it generates a signal. This signal can be used for the counter reset, to generate a timer
interrupt, for toggling the output flip-flop, as SSI clock or as clock for the next counter stage. For
each compare register, a compare-mode register exists. These registers contain mask bits to
enable or disable the generation of an interrupt, a counter reset, or an output toggling with the
occurrence of a compare match of the corresponding compare register. The mask bits for acti-
vating the single-action mode can also be located in the compare mode registers. When
assigned to the compare register a compare event will be suppressed.
T3CS
T3E1
T3E0
T3CS1 Timer 3 Clock Source select bit 1
T3CS0 Timer 3 Clock Source select bit 0
T3CS1
T3E1
1
1
0
0
1
1
0
0
Timer 3 Edge select bit 1
Timer 3 Edge select bit 0
Timer 3 Edge Select Bits
Timer 3 Clock Select Bits
Bit 3
T3E1
TCS0
T3E0
1
0
1
0
1
0
1
0
Bit 2
T3E0
Timer 3 Input Edge Select (T3I)
–
Positive edge at T3I pin
Negative edge at T3I pin
Each edge at T3I pin
Counter 3 Input Signal (CL3)
System clock (SYSCL)
Output signal of Timer 2 (POUT)
Output signal of Timer 1 (T1OUT)
External input signal from T3I edge detect
Bit 1
T3CS1
Bit 0
T3CS0
Address: "B"hex - Subaddress: "1"hex
Reset value: 1111b
ATAM862-4
69