ATAM862P-TNSY4D Atmel, ATAM862P-TNSY4D Datasheet - Page 89

• Manufacturer Part Number: ATAM862P-TNSY4D
• Description: IC MCU FLASH 4K TX 433MHZ 24SSOP
• Manufacturer: Atmel

Specifications of ATAM862P-TNSY4D

• Applications: UHF ASK/FSK
• Core Processor: MARC4
• Program Memory Type: FLASH (4 kB)
• Controller Series: MARC4 4-Bit
• Ram Size: 256 x 4
• Interface: SSI
• Number Of I /o: 11
• Voltage - Supply: 1.8 V ~ 4 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 24-SSOP
• Processor Series: ATAM862x
• Core: MARC4
• Data Bus Width: 4 bit
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

24.2.3
4551G–4BMCU–07/07
Combination Mode 8: Manchester Demodulation/Pulse-width Demodulation
SSI mode 1:
Timer 3 mode 10:
For Manchester demodulation, the edge detection stage must be programmed to detect each
edge at the input. These edges are evaluated by the demodulator stage. The timer stage is used
to generate the shift clock for the SSI. A compare register 1 match event defines the correct
moment for shifting the state from the input T3I as the decoded bit into shift register. After that,
the demodulator waits for the next edge to synchronize the timer by a reset for the next bit. The
compare register 2 can be used to detect a time error and handle it with an interrupt routine.
Before activating the demodulator mode the timer and the demodulator stage must be synchro-
nized with the bitstream. The Manchester code timing consists of parts with the half bitlength
and the complete bitlength. A synchronization routine must start the demodulator after an inter-
val with the complete bitlength.
The counter can be driven by any internal clock source. The output T3O can be used by Timer 2
in this mode. The Manchester decoder can also be used for pulse-width demodulation. The input
must programmed to detect the positive edge. The demodulator and timer must be synchronized
with the leading edge of the pulse. After that a counter match with the compare register 1 shifts
the state at the input T3I into the shift register. The next positive edge at the input restarts the
timer.
Figure 24-10. Manchester Demodulation
CM31=SCI
SR-DATA
Timer 3
mode
T3EX
T3I
SI
Synchronize
1
8-bit shift register internal data input (SI) and the internal shift clock
(SCI) from the Timer 3
Manchester demodulation/pulse-width demodulation with Timer 3
0
Bit 7
1
1
Bit 6
1
1
Manchester demodulation mode
Bit 5
1
1
0
Bit 4
0
0
Bit 3
0
Bit 2
1
1
ATAM862-4
Bit 1
1
1
Bit 0
0
0
89