ATAM862P-TNSY4D Atmel, ATAM862P-TNSY4D Datasheet - Page 38

• Manufacturer Part Number: ATAM862P-TNSY4D
• Description: IC MCU FLASH 4K TX 433MHZ 24SSOP
• Manufacturer: Atmel

Specifications of ATAM862P-TNSY4D

• Applications: UHF ASK/FSK
• Core Processor: MARC4
• Program Memory Type: FLASH (4 kB)
• Controller Series: MARC4 4-Bit
• Ram Size: 256 x 4
• Interface: SSI
• Number Of I /o: 11
• Voltage - Supply: 1.8 V ~ 4 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 24-SSOP
• Processor Series: ATAM862x
• Core: MARC4
• Data Bus Width: 4 bit
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

22.3
Figure 22-4. Port 5 External Interrupts
38
Bi-directional Port 5
ATAM862-4
BP52
BP53
Bidir. Port
Bidir. Port
IN_Enable
IN_Enable
Data in
Data in
As all other bi-directional ports, this port includes a bitwise programmable Control Register
(P5CR), which allows the individual programming of each port bit as input or output. It also
opens up the possibility of reading the pin condition when in output mode. This is a useful fea-
ture for self testing and for serial bus applications.
The port pins can also be used as external interrupt inputs (see
The interrupts (INT1 and INT6) can be masked or independently configured to trigger on either
edge. The interrupt configuration and port direction is controlled by the Port 5 Control Register
(P5CR). An additional low resistance pull-up/pull-down transistor mask option provides an inter-
nal bus pull-up for serial bus applications.
The Port 5 Data Register (P5DAT) is I/O mapped to the primary address register of address "5"h
and the Port 5 Control Register (P5CR) to the corresponding auxiliary register. The P5CR is a
byte-wide register and is configured by writing first the low nibble and then the high nibble (see
section
Figure 22-3. Bi-directional Port 5
P5CR:
I/O-bus
“Addressing Peripherals” on page
I/O Bus
P53M2 P53M1 P52M2 P52M1 P51M2 P51M1 P50M2 P50M1
I/O Bus
Master reset
IN enable
Decoder
(Data out)
P5DATy
D
S
Q
Decoder
INT1
Decoder
INT6
32).
*
Configurable
V
Decoder
DD
*
*
*
I/O-bus
Switched
pull-up
pull-down
*
*
Switched
Figure 22-3
Data in
Data in
IN_Enable
IN_Enable
V
Bidir. Port
Bidir. Port
DD
*
*
V
Static
pull-up
BP5y
Static
Pull-down
and
DD
BP51
BP50
4551G–4BMCU–07/07
Figure
22-4).