ATAM862P-TNSY4D Atmel, ATAM862P-TNSY4D Datasheet - Page 64

• Manufacturer Part Number: ATAM862P-TNSY4D
• Description: IC MCU FLASH 4K TX 433MHZ 24SSOP
• Manufacturer: Atmel

Specifications of ATAM862P-TNSY4D

• Applications: UHF ASK/FSK
• Core Processor: MARC4
• Program Memory Type: FLASH (4 kB)
• Controller Series: MARC4 4-Bit
• Ram Size: 256 x 4
• Interface: SSI
• Number Of I /o: 11
• Voltage - Supply: 1.8 V ~ 4 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 24-SSOP
• Processor Series: ATAM862x
• Core: MARC4
• Data Bus Width: 4 bit
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

23.3.4
23.3.5
64
ATAM862-4
Timer 3 – Mode 9: Pulse-width Modulation with the Shift Register
Timer 3 – Mode 10: Manchester Demodulation/Pulse-width Demodulation
The two compare registers are used for generating two different time intervals. The SSI internal
data output (SO) selects which compare register is used for the output pulse generation. In this
mode both compare- and compare-mode registers must be programmed for generating the two
pulse widths. It is also useful to enable the single-action mode for extreme duty cycles. Timer 2
is used as baudrate generator and for the trigger restart of Timer 3. The SSI must be supplied
with a toggle signal of Timer 2. The counter is driven by an internal or external clock source (see
“Combination Mode 7: Pulse-width Modulation (PWM)” on page
Figure 23-9. Pulse-width Modulation
For Manchester demodulation, the edge detection stage must be programmed to detect each
edge at the input. These edges are evaluated by the demodulator stage. The timer stage is used
to generate the shift clock for the SSI. The compare register 1 match event defines the correct
moment for shifting the state from the input T3I as the decoded bit into shift register - after that
the demodulator waits for the next edge to synchronize the timer by a reset for the next bit. The
compare register 2 can also be used to detect a time-out error and handle it with an interrupt
routine (see
page
Figure 23-10. Manchester Demodulation
89).
Counter 3
CM31=SCI
SR-DATA
Timer 3
TOG2
CM31
CM32
SCO
T3O
T3R
SIR
mode
T3EX
SO
T3I
SI
“Combination Mode 8: Manchester Demodulation/Pulse-width Demodulation” on
0 0 0 0 0 0 0 0 0
Synchronize
1
0
0
0 0 0 0
0
0 0 0 0 0 1 2 3 4 5 6 7 8 9 1011121314150 1 2 3 4 5
BIT 0
1
1
BIT 1
1
1
Manchester demodulation mode
1
BIT 2
1
1
0
BIT 3
0
88).
0
BIT 4
0
6 7 8
0
BIT 5
1
1
9
10
1112
13
BIT 6
4551G–4BMCU–07/07
1
14
1
15
0
1
0
2 3
0
1
4