ATAM862P-TNSY4D Atmel, ATAM862P-TNSY4D Datasheet - Page 88
![IC MCU FLASH 4K TX 433MHZ 24SSOP](/photos/6/76/67636/453-24-ssop_sml.jpg)
ATAM862P-TNSY4D
Manufacturer Part Number
ATAM862P-TNSY4D
Description
IC MCU FLASH 4K TX 433MHZ 24SSOP
Manufacturer
Atmel
Datasheet
1.ATAM862P-TNQY4D.pdf
(110 pages)
Specifications of ATAM862P-TNSY4D
Applications
UHF ASK/FSK
Core Processor
MARC4
Program Memory Type
FLASH (4 kB)
Controller Series
MARC4 4-Bit
Ram Size
256 x 4
Interface
SSI
Number Of I /o
11
Voltage - Supply
1.8 V ~ 4 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
24-SSOP
Processor Series
ATAM862x
Core
MARC4
Data Bus Width
4 bit
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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24.2.1
24.2.2
88
ATAM862-4
Combination Mode 6: FSK Modulation
Combination Mode 7: Pulse-width Modulation (PWM)
SSI mode 1:
Timer 3 mode 8:
The two compare registers are used to generate two varied time intervals. The SSI data output
selects which compare register is used for the output frequency generation. A "0" level at the
SSI data output enables the compare register 1 and a "1" level enables the compare register 2.
The compare and compare mode registers must be programmed to generate the two frequen-
cies via the output toggle flip-lop. The SSI can be supplied with the toggle signal of Timer 2 or
any other clock source. The Timer 3 counter is driven by an internal or external clock source.
Figure 24-8. FSK Modulation
SSI mode 1:
Timer 3 mode 9:
The two compare registers are used to generate two varied time intervals. The SSI data output
selects which compare register is used for the output pulse generation. In this mode, both com-
pare and compare mode registers must be programmed to generate the two pulse width. It is
also useful to enable the single-action mode for extreme duty cycles. Timer 2 is used as
baudrate generator and for the triggered restart of Timer 3. The SSI must be supplied with the
toggle signal of Timer 2. The counter is driven by an internal or external clock source.
Figure 24-9. Pulse-width Modulation
Counter 3
Counter 3
TOG2
CM31
CM32
SCO
CM31
CM32
T3O
T3R
SIR
SO
T3R
T3O
SO
0 0 0 0 0 0 0 0 0
0 1 2 3 4 0 1 2 3 4 0 1 2 0
8-bit shift register internal data output (SO) to the Timer 3
FSK modulation with shift register data (SO)
8-bit shift register internal data output (SO) to the Timer 3
Pulse-width modulation with the shift register data (SO)
0
0
0 0 0 0
0
0 0 0 0 0 1 2 3 4 5 6 7 8 9 1011121314150 1 2 3 4 5
1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 3 4 0
1
1
6 7 8
0
9
10
1112
13
4551G–4BMCU–07/07
0
14
1 2
15
0
3
1
4 0
2 3
1
4
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