ATAM862P-TNSY4D Atmel, ATAM862P-TNSY4D Datasheet - Page 98

• Manufacturer Part Number: ATAM862P-TNSY4D
• Description: IC MCU FLASH 4K TX 433MHZ 24SSOP
• Manufacturer: Atmel

Specifications of ATAM862P-TNSY4D

• Applications: UHF ASK/FSK
• Core Processor: MARC4
• Program Memory Type: FLASH (4 kB)
• Controller Series: MARC4 4-Bit
• Ram Size: 256 x 4
• Interface: SSI
• Number Of I /o: 11
• Voltage - Supply: 1.8 V ~ 4 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 24-SSOP
• Processor Series: ATAM862x
• Core: MARC4
• Data Bus Width: 4 bit
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

24.7.4
24.7.5
24.7.6
24.7.7
24.7.8
98
ATAM862-4
Write One Data Byte
Write Two Data Bytes
Write Control Byte Only
Write Control Bytes
Read Operations
A -> acknowledge; HB: high byte; LB: low byte; R: row address
The EEPROM allows byte-, word- and current address read operations. The read operations are
initiated in the same way as write operations. Every read access is initiated by sending the
START condition followed by the control byte which contains the address and the read mode.
When the device has received a read command, it returns an acknowledge, loads the addressed
word into the read/write buffer and sends the selected data byte to the master. The master has
to acknowledge the received byte if it wants to proceed the read operation. If two bytes are read
out from the buffer the device increments respectively decrements the word address automati-
cally and loads the buffer with the next word. The read mode bits determines if the low or high
byte is read first from the buffer and if the word address is incremented or decremented for the
next read access. If the memory address limit is reached, the data word address will roll over
and the sequential read will continue. The master can terminate the read operation after every
byte by not responding with an acknowledge (N) and by issuing a stop condition.
Write low byte first
Byte order
Write high byte first
Byte order
Start
Start
Start
Control byte
Control byte
Control byte
A
A
A
Data byte 1
Data byte 1
Stop
A4
A4
HB(R)
LB(R)
MSB
MSB
A3
A3
Row address
Row address
A
A
A2
A2
HB(R)
LB(R)
Stop
Data byte 2
A1
A1
A0
A0
A
C1
C1
Stop
0
1
C0
C0
1
0
R/NW
R/NW
LSB
LSB
0
0
4551G–4BMCU–07/07