PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 12
PNX1500E
Manufacturer Part Number
PNX1500E
Description
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1500E.pdf
(828 pages)
Specifications of PNX1500E
Lead Free Status / Rohs Status
Not Compliant
Available stocks
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Part Number
Manufacturer
Quantity
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Company:
Part Number:
PNX1500E
Manufacturer:
NORTEL
Quantity:
1 000
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NXP Semiconductors
Volume 1 of 1
Chapter 24: TM3260 Debug
1.
1.1
2.
2.1
2.1.1
2.1.2
2.1.3
Chapter 25: I
1.
1.1
2.
2.1
2.1.1
2.1.2
2.1.3
2.1.4
Chapter 26: Memory Arbiter
1.
1.1
2.
2.1
2.2
2.2.1
2.3
Chapter 27: Power Management
1.
1.1
1.1.1
Chapter 28: Pixel Formats
1.
2.
3.
3.1
3.2
3.3
3.4
3.5
3.5.1
Chapter 29: Endian Mode
1.
1.1
2.
PNX15XX_PNX952X_SER_N_4
Product data sheet
Introduction
Functional Description
Introduction
Functional Description
Introduction
Functional Description
Power Management Mechanisms
Introduction
Summary of Native Pixel Formats
Native Pixel Format Representation
Introduction
Functional Description
Features
General Operations
Test Access Port (TAP)
TAP Controller
PNX15xx/952x Series JTAG Instruction Set
Features
General Operations
IIC Arbitration and Control Logic
Serial Clock Generator
Bit Counter
Control Register
Features
Arbiter Features
ID Mapping
DCS Gate
Arbitration Algorithm
Clock Management
Essential Operating Infrastructure During
Powerdown
Indexed Formats
16-Bit Pixel-Packed Formats
32-Bit Pixel-Packed Formats
Packed YUV 4:2:2 Formats
Planar YUV 4:2:0 and YUV 4:2:2 Formats
Planar Variants
Features
2
C Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760
785
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 748
. . . . . . . . . . . . . . . . . . . . . . . . . . . 793
. . . . . . . . . . . . . . . . . . . . . . . . . . 760
. . . . . . . . . . . . . . . . . . . . . . . . . . 777
. . . . . . . . . . . . . . . . . . . . . . . . . . 790
. . . . . . . . . . . . . . . . . . . . . . . 747
. . . . . . . . . . . . . . . . . . . . . . . 759
. . . . . . . . . . . . . . . . . . . . . . . 785
. . . . . . . . . . . . . . . . . . . . . . 778
. . . . . . . . . . . . . . . . . . . . 747
. . . . . . . . . . . . . . . . . . . . 760
. . . . . . . . . . . . . . . . . . 747
. . . . . . . . . . . . . . . . . . 759
. . . . . . . . . . . . . . . . . . 776
. . . . . . . . . . . . . . . . . . 802
. . . . . . . . . . . . . . . . 792
. . . . . . . . . . . . . . . 791
. . . . . . . . . . . . . . . 791
. . . . . . . . . . . . 759
. . . . . . . . 785
Rev. 4.0 — 03 December 2007
. . . . . . . 789
. . . . . 790
. . . 793
. . 750
3.
3.1
3.1.1
3.2
4.
4.1
2.1.5
2.1.6
2.1.7
2.1.8
2.1.9
2.1.10
3.
3.1
2.3.1
3.
3.1
3.2
4.
4.1
1.1.2
1.1.3
1.1.4
1.1.5
3.5.2
3.5.3
4.
5.
6.
7.
8.
2.1
3.
3.1
Operation
Register Descriptions
Register Descriptions
Operation
Register Descriptions
Universal Converter
Alpha Value and Pixel Transparency
RGB and YUV Values
Image Storage Format
System Endian Mode
Endian Mode Theory
PNX15xx/952x Series
Register Programming Guidelines
Handshaking and Communication Protocol
Debug Settings
Register Summary
Status Decoder and Register
Input Filter
Address Register and Comparator
Data Shift Register
Related Interrupts
Modes of Operation
Register Tables
Arbiter Startup Behavior
Clock Programming
Register Programming Guidelines
Register Table
Module Powerdown Sequence
Peripheral Module Wakeup Sequence
TM3260 Powerdown Modes
SDRAM Controller
Semi-Planar 10-Bit YUV 4:2:2 and 4:2:0 Formats
796
Packed 10-bit YUV 4:2:2 format
Endian Mode System Block Diagram
Law 1: The “CPU Rule”
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781
. . . . . . . . . . . . . . . . . . . . . . . . . . . 782
Connected Media Processor
. . . . . . . . . . . . . . . . . . . . . . . . . . 752
. . . . . . . . . . . . . . . . . . . . . . . . . . 765
. . . . . . . . . . . . . . . . . . . . . . . . 761
. . . . . . . . . . . . . . . . . . . . . . . . 787
. . . . . . . . . . . . . . . . . . . . . . . 755
. . . . . . . . . . . . . . . . . . . . . . . 761
. . . . . . . . . . . . . . . . . . . . . . 761
. . . . . . . . . . . . . . . . . . . . . . 781
. . . . . . . . . . . . . . . . . . . . . 797
. . . . . . . . . . . . . . . . . . . . 804
. . . . . . . . . . . . . . . . . . . 753
. . . . . . . . . . . . . . . . . . . 764
. . . . . . . . . . . . . . . . . . . 781
. . . . . . . . . . . . . . . . . . . 782
. . . . . . . . . . . . . . . . . . . 798
. . . . . . . . . . . . . . . . . . . 799
. . . . . . . . . . . . . . . . . . . 804
. . . . . . . . . . . . . . . . . . 798
. . . . . . . . . . . . . . . 786
© NXP B.V. 2007. All rights reserved.
. . . . . . . . . . . . . . 760
. . . . . . . . . . . . . 785
. . . . . . . . . . . . 797
. . . . . . . . . . 750
. . . . . . . . . . 781
. . . . . . . . . 760
. . . . . . . 802
. . . . . . 786
. . . . 798
. . 751
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