PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 760

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
PNX15XX_PNX952X_SER_N_4
Product data sheet
2.1.2 Serial Clock Generator
2.1.3 Bit Counter
2.1.4 Control Register
2.1.5 Status Decoder and Register
2.1.6 Input Filter
2.1.7 Address Register and Comparator
A slave may stretch the space duration to slow down the bus master. The space
duration may also be stretched for handshaking purposes. This can be done after
each bit or after a complete byte transfer. The IIC module will stretch the SCL space
duration after a byte has been transmitted or received and the acknowledge bit has
been transferred. This block also controls all of the signals for serial byte handling. It
provides the shift pulses for DAT, enables the comparator, generates and detects
START and STOP conditions, receives and transmits acknowledge bits, controls the
master and slave modes, contains interrupt request logic and monitors the I
status.
This programmable clock pulse generator provides the SCL clock pulses when the
IIC module is in master transmitter or master receiver mode. It is switched off when
the IIC module is in a slave mode. The output frequency is dependent on the CR bits
in the control register. The output clock pulses have a 50% duty cycle unless the
clock generator is synchronized with other SCL clock sources, as described above.
The bit counter tracks the number of bits that have been received during the byte
transfer. The output from this counter is used to trigger events, such as address
recognition and acknowledge generation, which occur at specific points during the
byte transfer.
This register is used by the micro controller to control the generation of START and
STOP conditions, enable the interface, control the generation of ACKs, and to select
the clock frequency.
There are 26 possible bus states if all four modes of the IIC module are used. The
status decoder takes all of the internal status bits and compresses them into a 5-bit
code. This code is unique for each I
processing the various service routines. Each service routine processes a particular
bus status. The 5-bit status code is stored in bits 7-3 of the status register. Bits 2-0
and 31-8 of the status register are always zero.
Input signals SDA and SCL from IO pad cells are synchronized with the internal
clock. Spikes shorter than three clock periods are filtered out.
This SFR may be loaded with the 7-bit slave address to which IIC module will
respond when programmed as a slave. The least significant bit is used to enable the
general call address recognition. The comparator compares the received 7-bit slave
address with its own slave address. It also compares the first received 8-bit byte with
the general call address. If an equality is found, the appropriate status bits are set
and an interrupt is requested.
Rev. 4.0 — 03 December 2007
2
C bus status. The 5-bit code may be used for
PNX15xx/952x Series
Chapter 25: I
© NXP B.V. 2007. All rights reserved.
2
C Interface
2
C bus
25-760