PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 485

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
PNX15XX_PNX952X_SER_N_4
Product data sheet
Figure 1:
MMIO/DCS Bus
Top Level Block Diagram
VDI Pads
32
1.1 FGPI Overview
Refer to
module to the MMIO and MTL Busses within the PNX15xx/952x Series. All external
FGPI signals are registered and routed through the Input Router module before being
presented to the FPGI module. Latency buffering of data and endian conversion is
done in the MTL DTL Adapter. All FGPI register access is through the MMIO DTL
adapter.
Input Router
Clock Block
Figure
1. This block diagram shows the top level connection of the FGPI
32
Rev. 4.0 — 03 December 2007
32
Chapter 14: FGPI: Fast General Purpose Interface
32
32
PNX15xx/952x Series
© NXP B.V. 2007. All rights reserved.
64
MTL Bus
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