PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 393

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
PNX15XX_PNX952X_SER_N_4
Product data sheet
4.8.1 Layer Underflow
4.8.2 Underflow Symptom
4.8.3 Underflow Recovery
4.8.4 Underflow Trouble-shooting
4.8.5 Underflow Handling
4.9 Setting QVCP for External VSYNC
Any time the layer position has reached but the small 16-pixel FIFO at the end of
every layer pipe has run out of available pixels, underflow occurs.
Should an underflow occur, the layer would fetch and dump remaining data for the
current field/frame. The next field/frame would be fetched and displayed as normal.
The underflow interrupt status would stay asserted until an interrupt-status-clear is
programmed.
Set the following bits in MMIO register 0x10,E020 as follows:
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Only portion of a picture is displayed or occasional blinking of picture happens
Underflow interrupt bit is set.
Check if the DMA source width settings (0x10,Ex08) matches the initial layer
width (0x10,Ex34)
Check if the initial layer width (0x10,Ex34) matches the final layer width
(0x10,ExB4) for the non-scaled layer.
Check if the final layer width (0x10,ExB4) is within acceptable cropping range for
LINT or HSRU scaling.
Check whether the DMA start fetch (0x10,ExC8) is at line number too close to the
display position. Note that about 64 pixels is QVCP’s input-to-output latency. So,
depending on the system-memory latency, the DMA fetch should start as early as
possible, in order to make up for the request-to-data latency.
Check if the system memory arbiter is giving high priority to QVCP.
Check if QVCP demands exceed allocated memory bandwidth.
bit 1 (master) = 1;
bit 2 (Trigger_pol) = 1; for posisitive edge trigger
bit 16 (SYNCCtl) = 0; VSYNC pin becomes an input
bit 24 (VSYNCPol) = 0;
Rev. 4.0 — 03 December 2007
PNX15xx/952x Series
Chapter 11: QVCP
© NXP B.V. 2007. All rights reserved.
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