PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 69
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PNX1500E
Manufacturer Part Number
PNX1500E
Description
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1500E.pdf
(828 pages)
Specifications of PNX1500E
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Volume 1 of 1
Table 44: GPIO Timing
PNX15XX_PNX952X_SER_N_4
Product data sheet
Symbol
F
T
T
T
T
T
CLOCK
CLK-DV1
CLK-DV2
SU-CLK
H-CLK
VALID
Parameter
GPIO sampling/pattern generation CLOCK frequency
GPIO[6:0] CLOCK to DATA valid for GPIO[15:0] pins
GPIO[6:0] CLOCK to DATA valid for GPIO[60:16] pins
Input setup time
Input hold time
Valid time required for sampling mode, i.e. F
7.12 GPIO Interface
[44-1]
[44-2]
[44-3]
Figure 20: I
Notes:
1. The GPIO module can operate up to 108 MHz, however the maximum operating
frequency may be limited due to the wide variation of T
window is required for data out then the maximum recommended operating frequency is 50
MHz for T
2. Timing applies whether the data is output on a positive or negative edge. GPIO[6:0] can
be selected as clocks. Data can be any of the GPIO[60:0] as defined in
page
1-27.
2
C I/O Timing
CLK-DV2
Rev. 4.0 — 03 December 2007
II_CSDA
IIC_SCL
IIC_SDA
IIC_SCL
and 65 MHz for T
IIC_SDA
IIC_SCL
CLOCK
T
DV-SDA
/8
T
SU-STA
CLK-DV1
T
SU-SDA
Min
3.5
3
6.5
1.5
75
.
valid
valid
PNX15xx/952x Series
Chapter 1: Integrated Circuit Data
T
CLK-DV[1,2]
H-STA
T
DV-STO
Max
108
15
17.5
T
H-SDA
. For example if a 4 ns valid
Units
MHz
ns
ns
ns
ns
ns
Section 2.3 on
© NXP B.V. 2007. All rights reserved.
Notes
1
1
1
2
2
1-69
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