PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 272

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
PNX15XX_PNX952X_SER_N_4
Product data sheet
2.1.3 GPIO Pin Status Reading
2.2 GPIO: The Event Monitoring Mode
Each GPIO pin can be read by software using an MMIO read of the proper MASK and
IOD register. In the 32-bit register, the lower 16 bits are the GPIO pin data values.
Software reading of the GPIO input pins is always possible, even when the GPIO pin
is operating in its primary function mode.
Remark: For open drain or tri-state output values, the input value read by software is
the pad value, not the driven value.
The GPIO module allows to monitor events on all 61 GPIO pins but also on some
PNX15xx/952x Series internal signals coming from the different modules of
PNX15xx/952x Series. These signals are usually signals indicating the end or the
start of the capture of a buffer. Documentation on the following signals can be found
on each module documentation.
The state of these internal signals can be observed by software at any time by
consulting the Internal Signals MMIO register documented in
PNX15xx/952x Series integrates a total of 12 timestamp units for event monitoring.
An event is defined by a change on the monitored signals, i.e. a high to low or a low to
high transition is an event. The operating mode of the timestamp units is simple:
•
•
•
•
•
•
•
•
•
VIP timestamp: vip1_eow_vbi, vip_eow_vid
AI timestamp: ai1_tstamp
AO timestamp: ao1_tstamp
SDPI: spdi_tstamp1, spdi_tstamp2 (See SPDI MUX in
page
SPDO: spdo_tstamp
GPIO timestamps: LAST_WORD[3:0]
QVCP timestamp: qvcp_tstamp
The software running on TM3260 selects the internal signals or the GPIO pins to
be event monitored by setting properly the GPIO_EV[15:4] MMIO registers.
These 12 control registers (one per timestamp unit) are used to select the source
to monitor, the type of the event (rising, falling edge or both) as well as enabling
the capture of the event.
Every time an event occurs a DATA_VALID interrupt is generated. Therefore the
DATA_VALID interrupt condition needs to be enabled by writing to the
INT_ENABLE4 MMIO register (the GPIO generates the interrupt through
interrupt line 4 which is connected to the TM3260, see
SOURCE number allocation). The INT_STATUS4 MMIO register indicates which
of the 12 units has data ready to consume. The GPIO module expects then an
interrupt clear by writing to the INT_CLEAR4 MMIO register.
3-135)
Rev. 4.0 — 03 December 2007
Chapter 8: General Purpose Input Output Pins
PNX15xx/952x Series
Section 8.1 on
Table 5 on page 3-120
Section
© NXP B.V. 2007. All rights reserved.
4.3.
8-272
for