PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 318

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
PNX15XX_PNX952X_SER_N_4
Product data sheet
Figure 4:
Arbitration when DMA has priority
DMA request
handle
any request in BLB
2.2.2 Second Level of Arbitration
2.2.3 Dynamic Ratios
DMA request
DMA request
from BLB
handle
begin
This equilibrium is only possible with CPU_DECR = 1 and all transfers back-to-back
without any efficiency loss. In other words: when the CPU account exceeds the
CPU_CLIP value, the account can only stay constant when the CPUs take 100% of
the available bandwidth. This is unlikely to happen because the CPU account
exceeds the CPU_LIMIT value, giving DMA a higher priority than the CPUs.
Therefore, the CPU account will not stay above CPU_CLIP for long.
The accounting mechanism described earlier is the static ratio variant. The problem
with this approach is that the statically programmed CPU_RATIO that is used, per
DDR burst, can not account for significantly different amounts of overhead by a DDR
burst that can occur in real life. To fix that problem dynamic ratios have been
introduced, which can be enabled through the ARB_CTL register.
high priority in budget CPU
least recently handled
1 high priority CPU
is requesting
in budget
handle
Rev. 4.0 — 03 December 2007
low priority in budget CPU
least recently handled
1 low priority CPU
is requesting
in budget
end
handle
least recently handled
1 high priority CPU
high priority CPU
out of budget
is requesting
handle
PNX15xx/952x Series
least recently handled
1 low priority CPU
low priority CPU
out of budget
is requesting
Chapter 9: DDR Controller
handle
© NXP B.V. 2007. All rights reserved.
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