PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 743

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
Table 12: LAN100 Pin Interface to external PHY
PNX15XX_PNX952X_SER_N_4
Product data sheet
Pin
LAN_RX_ER
LAN_MDIO
LAN_MDC
6.2.1 Sleep Mode
6.2.2 Coma Mode
6.2 Power Management
The LAN100 supports power management by means of external clock switching.
Basically, all clocks in the LAN100 module can be switched off. If WoL is needed, the
receive clock should not be switched off.
The LAN100 supports two power management modes:
The LAN100 can be put in sleep mode by setting the PowerDown bit in the
PowerDown register if the receive and transmit DMA managers are disabled and
inactive. Clocks should only be disabled after software has set the PowerDown bit.
Software should prevent access to components of the LAN100 that have been
switched off. If an external PHY is connected, a WoL can still trigger an interrupt.
To enter sleep mode, software should:
If no PHY is connected software can directly set the PowerDown bit and disable the
clocks.
To exit sleep mode sofware should:
In coma mode, most of the clocks in the PNX15xx/952x Series can be switched off
including the CPU and MMIO clocks. If an external PHY is connected, the receive
filter and WoL detection will still be active and capable of generating a WoL interrupt
to the system’s power-management controller.
•
•
•
•
•
•
•
Directio
n
In
In/Out
Out
Sleep mode : the PNX15xx/952x Series is active while most clocks are switched
off. The CPU is active and can still communicate with the LAN100 via MMIO
registers.
Coma mode : most of the clocks in the PNX15xx/952x Series are switched off,
including the LAN100, CPU, and MMIO clock.
Disable both transmit DMA managers and the receive DMA manager by writing
the Command register
Wait for the transmit and Receive Datapaths to be inactive by waiting for a
Finished interrupt or by polling the Status register.
Set the PowerDown bit by writing to the PowerDown register.
Reset the PowerDown bit
Reenable the receive and Transmit Datapaths.
Description
MII or RMII Receive Error
MII Management data I/O
MII Management Data clock
Rev. 4.0 — 03 December 2007
…Continued
Chapter 23: LAN100 — Ethernet Media Access Controller
PNX15xx/952x Series
© NXP B.V. 2007. All rights reserved.
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