PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 327

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
PNX15XX_PNX952X_SER_N_4
Product data sheet
Unhalting/warm start done
Figure 7:
DDR SDRAM Controller Start and Halt State Machine
Halting done
MMIO halt
2.5.4 Observing Halt Mode
Initialization done
Unhalting
MMIO warm start
Halting
to be turned on before the MTL memory request is presented to the DDR controller).
This mode adds extra latency for requests to be served and should therefore be used
adequately.
state
When the DDR SDRAM Controller entered halt mode due to an auto halt, it will only
unhalt when a MTL memory request is presented to one of its input ports. To ensure
the DDR controller can detect these MTL memory requests, the DDR controller clock
inputs need to be turned on during auto-halt (or at least turned on before the MTL
memory request is presented to the DDR controller). Therefore it is advised not to
turn off the clock to the DDR controller when “ip_2031_auto_halted“ is ‘1’ since this is
a dynamic mode controlled by the DDR controller not software.
The DDR SDRAM Controller is in halt mode if the HALT_STATUS bit in the MMIO
register IP_2031_CTL is set to ‘1’. The clock, clk_mem and clk_mmio must be turned
on to execute the MMIO read.
state
state
Halt
Rev. 4.0 — 03 December 2007
Initialization
Running
Reset
state
state
state
MMIO start
“ip_2031_auto_halted = 1”
Hard reset
MMIO auto halt
Unhalting
PNX15xx/952x Series
Halting
state
state
state
Halt
Halting done
Unhalting done
MMIO unhalt
& valid MTL command
Chapter 9: DDR Controller
“ip_2031_halted = 1”
© NXP B.V. 2007. All rights reserved.
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