PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 163
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PNX1500E
Manufacturer Part Number
PNX1500E
Description
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1500E.pdf
(828 pages)
Specifications of PNX1500E
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Volume 1 of 1
PNX15XX_PNX952X_SER_N_4
Product data sheet
Figure 3:
CAB
Block Diagram of the Clock Control Logic
2.3 Clock Control Logic
re-program PLL
parameters or
1.728 GHz PLL
divider
BLOCKING
Logic
All the generated PNX15xx/952x Series clocks follow the generic block diagram
presented in
normal functional operating mode.
The clock module allows several clock sources per clock signal. The different clock
sources are selected with a multiplexer. In order to guaranty a glitch free dynamic
clock switch a blocking block is added after the clock multiplexer.
The same blocking mechanism is necessary when the PLL control register is re-
programmed since the PLL clock needs first to be stable, i.e. locks, before it can be
used by any module. So the PLL clock is first blocked by the blocking circuit before
the new PLL parameters are passed to the PLL. The Blocking circuit will block the
clock output when the turn_off signal is set by the blocking logic. The clock is blocked
after a falling edge to ensure the clock is held low. Once the blocking circuit has
blocked the clock, the turn_off_ack signal is set to high, and it is then safe to pass the
new parameters to the PLL.
clk_out
“second_clk”
ext_clk
/n
Figure
n = 2,3,4,5,6
xtal_clk
Rev. 4.0 — 03 December 2007
3. The signals in
clock divider
re-program
BLOCKING
Logic
red
exit_reset reg is set
or testmode
switch mux if:
are for ATE purpose and are disabled in
tst_clk_x
tst_clk_sel
PNX15xx/952x Series
CLOCK CONTROL LOGIC SLICE
Chapter 5: The Clock Module
© NXP B.V. 2007. All rights reserved.
clock_out
slice_tst_out
5-163
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