PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 239

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
5. Register Descriptions
PNX15XX_PNX952X_SER_N_4
Product data sheet
4.3.4 IDE Interface
4.4 PCI Endian Support
4.5 General Notes
In this XIO mode, an IDE disk drive can be addressed. Only PIO mode is supported.
The internal DMA engine can be programmed to perform data transfer to and from
the IDE once the disk drive’s registers have been programmed. The DIOR and DIOW
strobe high and low times are programmable. Refer to
for more details.
The IDE interface is internally grouped with 16bit XIO devices. This restricts the
software in direct and indirect IDE register access to using 16 or 32 bit opcodes for
writes and reads. These are mapped to a single write or read on accessing the IDE
drive.
The PCI module supports both big-endian and little-endian systems. The global
system endian mode signal is used to determine which endian mode is in use.
The cache line size register (PCI configuration register C) should be initialized to a
non-zero value larger than the “slv_threshold” (Slave DTL tuning register) if using
cache line read commands in the system. See note on recommended slv_threshold
setting in the register description.
The following section describes the registers in the PCI-XIO block. The PCI
configuration registers and the memory mapped IO registers are included.
Rev. 4.0 — 03 December 2007
PNX15xx/952x Series
Section 3.1.4 IDE Description
Chapter 7: PCI-XIO Module
© NXP B.V. 2007. All rights reserved.
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