PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 636

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
Table 17: Color Compare
PNX15XX_PNX952X_SER_N_4
Product data sheet
Bit
Offset 0x04 F41C
31:24
23:16
15:8
7:0
Symbol
CCCol[31:24]
CCCol[23:16]
CCCol[15:8]
CCCol[7:0]
Color Compare
This register holds the offset between adjacent scanlines for BLTs and vectors. Under
many circumstances, this register will be initialized to the screen pitch and then
changed only for special effects. It is interpreted as an unsigned byte value.
This 14-bit signed register is used during BLTs and vectors to step from scanline to
scanline. It is also used to convert a DstXY address to a DstLinear address according
to the following formula:
DstLinear = DstXY.Y * DstStride + DstXY.X
There are no restrictions on this register except that the lower three bits are always
interpreted as 0, regardless of the value written. When reading the contents of this
register, the lower three bits will be read back as 0. This implies that the destination
stride must be a multiple of 8 bytes.
As an unsigned register, it is always interpreted as a positive value. The direction in
which the destination is traversed is controlled by the BLT direction field in the BltCtl
register.
This register may be useful for BLTing bitmaps stored in offscreen memory in a 1D
format to the screen. It is unchanged by drawing operations.
This register holds the color compare target color. This register should be initialized
prior to any BLT that enables color compare. The appropriate number of bytes needs
to be loaded in accordance with the current color depth. Thus, if the current depth is 8
bits, only the lowest byte need be written. If the depth is 16 bits, the lowest two bytes
need to be written.
When reading the value of this register, the lower byte will be replicated in all four byte
lanes in 8 bpp mode. In 16 bpp mode, the lower word will be replicated into the upper
word. In 32 bpp mode, all bits are unique and will read back the 32-bit data that was
written. This register is unchanged by drawing operations.
(1)
Acces
s
R/W
R/W
R/W
R/W
This value is adjusted for pixel color depth
Value
0
0
0
0
Rev. 4.0 — 03 December 2007
Description
Holds the color compare target color.
(1)
+ DstAddrBase
PNX15xx/952x Series
Chapter 20: 2D Drawing Engine
© NXP B.V. 2007. All rights reserved.
20-636