PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 395

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
5. Register Descriptions
Table 19: Register Module Association
PNX15XX_PNX952X_SER_N_4
Product data sheet
Offset
0x10 E000
0x10 E004
0x10 E008
0x10 E00C
0x10 E010
Control and Interrupt Registers
0x10 E014
0x10 E018
0x10 E01C
0x10 E020
0x10 E024
0x10 E028
0x10 E02C
0x10 E030
0x10 E034
0x10 E038
0x10 E03C
0x10 E040
0x10 E044
0x10 E048
0x10 E04C
0x10 E050
0x10 E054
0x10 E058
0x10 E05C
0x10 E060
0x10 E064
0x10 E068
0x10 E06C
0x10 E070
0x10 E074
TOTAL
HBLANK
VBLANK
HSYNC
VSYNC
VINTERRUPT
FEATURES
DEFAULT BACKGROUND COLOR
CONTROL
FINAL_LAYER_ASSIGNMENT
INTLCTRL1
Reserved
VBI SRC Address
VBI_CTRL
VBI_SENT_OFFSET
OUT_CTRL
POOL_RESOURCE_ID
POOL_RESOURCE_LAYER_ASSIGNMENT
RESOURCE_ID
FU_ASSIGNMENT
Signature1
Signature2
Signature3
Output pedestals1
Output pedestals2
Output GNSH LUT Data Upper
Output GNSH LUT Data Middle
Output GNSH LUT Data Lower
Output ONSH Ctrl
Output GAMMA Ctrl
Symbol
5.1 Register Summary
Table 19
relative to the MMIO_BASE. Only Layer 1 MMIO registers are displayed. Layer 2
MMIO registers are similar to Layer 1 MMIO registers but are located at offset
0x10E400 instead of 0x10E200.
summarizes the MMIO registers of QVCP. The offset are absolute offset
Rev. 4.0 — 03 December 2007
PNX15xx/952x Series
Module
Chapter 11: QVCP
© NXP B.V. 2007. All rights reserved.
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