PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 738

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
PNX15XX_PNX952X_SER_N_4
Product data sheet
Figure 15: Transmit Active/Inactive state machine
TxProduceIndex != TxConsumeIndex
5.14.2 Enabling and Disabling Transmission
5.15 Transmission Padding and CRC
After a reset, the FSM is in the INACTIVE state. As soon as the RxEnable bit is set in
the Command register, the FSM transitions to the ACTIVE state. As soon as the
RxEnable bit is cleared, the FSM returns to the INACTIVE state. If the Receive
Datapath is busy receiving a packet when it is put in the disabled state, packet
reception will continue and the packet will be received completely and stored to
memory along with its status before it returns to the INACTIVE state.
As shown in
is inactive until the datapath is re-enabled.
After reset, the transmit function of the LAN100 is disabled. The Transmit Datapaths
(Tx and TxRt) must be enabled separately. The device driver enables the Tx datapath
by setting the TxEnable bit in the Command register to 1. The device driver enables
the TxRt datapath by setting the TxRt bit in the Command register to 1.
The status of the Transmit Datapaths can be monitored by the device driver by
reading the TxStatus and TxRtStatus bits of the Status register. The FSM for both Tx
and TxRt are the same, as shown in
After reset, the FSMs are in the INACTIVE state. As soon as the Tx(Rt)Enable bit is
set in the Command register and the Produce and Consume indices are not equal,
the FSM transitions to the ACTIVE state. As soon as the Tx(Rt)Enable bit is cleared
and the Transmit Datapath has completed all pending transmissions including
committing the transmission status to memory, the FSM returns to the INACTIVE
state. The FSM will also return to the INACTIVE state if the Produce and Consume
indices are equal again, that is, when all packets have been transmitted.
As shown in
Section
In the event that a packet is received with a length of less than 60 bytes (or 64 bytes
for VLAN frames) the LAN100 can pad the packet to 64 or 68 bytes, including a
4-byte CRC Frame Check Sequence (FCS). Padding is affected by the value of the
5.19.2) until the datapath is re-enabled.
TxEnable &&
Figure
Figure
Reset
Rev. 4.0 — 03 December 2007
14, after a soft reset (see
15, the Transmit Datapath is inactive after a soft reset (see
Chapter 23: LAN100 — Ethernet Media Access Controller
RxStatus=1
RxStatus=0
INACTIVE
ACTIVE
Figure
(!TxEnable && not busy transmitting) ||
TxProduceIndex == TxConsumeIndex
15. .
Section
PNX15xx/952x Series
5.19.2), the Receive Datapath
© NXP B.V. 2007. All rights reserved.
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