PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 765

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
Table 2: IIC Registers
PNX15XX_PNX952X_SER_N_4
Product data sheet
Offset 0x04 5000
31:8
7
6
5
4
3
2:0
Bit
Symbol
Unused
AA
EN
STA
STO
Unused
CR
3.1 Register Tables
I2C CONTROL
Bit 7: AA Address Acknowledge
If the AA flag is set, an acknowledge (low level to SDA) will be returned during the
acknowledge clock pulse on the SCL line when:
•
•
•
•
The “own slave address” has been received.
The general call address has been received while the general call bit (GC) in the
ADR register is set.
A data byte has been received while IIC module is in the master receiver mode.
A data byte has been received while IIC module is in the addressed slave
receiver mode.
Acces
s
R/W
R/W
R/W
R
R/W
Value
-
0
0
0
0
-
100
Rev. 4.0 — 03 December 2007
Description
Ignore upon read. Write as zeroes.
IIC acknowledge bit
IIC enable bit
IIC start bit
IIC stop bit
Ignore upon read. Write as zeroes.
These three bits determine the serial clock frequency when
IIC module is in master mode. This field shall be changed
only when EN bit is 0.
achieve the desired frequency. The table assumes the IIC module
receives a 24 MHz clock from the Clock module.
0: 60 -> 400 KHz
1: 80 -> 300 KHz
2: 120 -> 200 KHz
3: 160 -> 150 KHz
4: 240 -> 100 KHz
5: 320 -> 75 KHz
6: 480 -> 50 KHz
7: 960 -> 25 KHz
0 = Acknowledge not returned during acknowledge clock pulse
1 = Acknowledge returned during acknowledge clock pulse
0 = Disable IIC module
1 = Enable IIC module
0 = Slave mode, accept transactions
1 = Master mode, generate start condition if bus is free
0 = Slave mode, accept transactions
1 = Generate stop condition on I
master.
The IIC Clock is divided as follows to
PNX15xx/952x Series
2
C bus when IIC module is
Chapter 25: I
© NXP B.V. 2007. All rights reserved.
2
C Interface
25-765