PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 675
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PNX1500E
Manufacturer Part Number
PNX1500E
Description
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1500E.pdf
(828 pages)
Specifications of PNX1500E
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NXP Semiconductors
Volume 1 of 1
PNX15XX_PNX952X_SER_N_4
Product data sheet
The register map of the LAN100 includes MII Interface registers and registers for
controlling DMA transfers, flow control and filtering. It also includes interrupt control
and module ID registers.
Table 1: LAN100 MMIO Register Map
Offset
MII Interface
0x07 2000
0x07 2004
0x07 2008
0x07 200C
0x07 2010
0x07 2014
0x07 2018
0x07 201C
0x07 2020
0x07 2024
0x07 2028
0x07 202C
0x07 2030
0x07 2034
0x07 2038
0x07 203C
0x07 2040
0x07 2044
0x07 2048
0x07 204C
to
0x07 20FC
Control Registers
0x07 2100
0x07 2104
0x07 2108
0x07 210C
0x07 2110
0x07 2114
0x07 2118
0x07 211C
0x07 2120
Name
MAC1
MAC2
IPGT
IPGR
CLRT
MAXF
SUPP
TEST
MCFG
MCMD
MADR
MWTD
MRDD
MIND
SA0
SA1
SA2
Command
Status
RxDescriptor
RxStatus
RxDescriptorNumber
RxProduceIndex
RxConsumeIndex
TxDescriptor
TxStatus
Rev. 4.0 — 03 December 2007
Chapter 23: LAN100 — Ethernet Media Access Controller
Table 1
provides a summary of all LAN100 registers.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
WO
RO
RO
R/W
R/W
R/W
R/W
RO
R/W
R/W
R/W
RO
R/W
R/W
R/W
Function
MAC Configuration register 1
MAC Configuration register 2
Back-to-back Inter-packet Gap register
Non B2B Inter-packet Gap register
Collision Window / Retry register
Maximum frame register
PHY Support register
Test register
MII Management Configuration register
MII Management Command register
MII Management Address register
MII Management Write Data register
MII Management Read Data register
MII Management Indicators register
Reserved
Reserved
Station Address 0 register
Station Address 1 register
Station Address 2 register
Reserved
Command register
Status register
Receive Descriptor Base Address register
Receive Status Base Address register
Number of Receive Descriptors register
Receive Produce Index register
Receive Consume Index register
Non Real-Time Transmit Descriptor Base
Address register
Non Real-Time Transmit Status Base Address
register
PNX15xx/952x Series
© NXP B.V. 2007. All rights reserved.
23-675
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