PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 576

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
Table 6: SPDIF Input Registers
PNX15XX_PNX952X_SER_N_4
Product data sheet
Bit
Offset 0x10 A034
31:0
Offset 0x10 A038
31:0
Offset 0x10 A03C
31:0
Offset 0x10 A040
31:0
Offset 0x10 A044
31:0
Offset 0x10 A048—AFDC Reserved
Offset 0x10 AFE0
31:10
9
8
Symbol
UBITS [31:0]
UBITS [31:0]
UBITS [31:0]
UBITS [31:0]
UBITS [191:159]
Unused
UNLOCK
UCBITS
SPDI_UBITS2
SPDI_UBITS3
SPDI_UBITS4
SPDI_UBITS5
SPDI_UBITS6
SPDI_STATUS
…Continued
Acces
s
R
R
R
R
R
R
R
Value
0
0
0
0
0
-
0
0
Rev. 4.0 — 03 December 2007
Description
User bit 2 contains the state of user bytes 4, 5, 6 and 7 of the block
according to SPDI_CTL.UCBITS_SEL. The SPDI_UBITS register
will always reflect the condition of the current decoded block of 192
frames. Register bit meaning will depend upon the source
transmission.
User bit 3 contains the state of user bytes 8, 9, 10 and 11 of the
block according to SPDI_CTL.UCBITS_SEL. The SPDI_UBITS
register will always reflect the condition of the current decoded block
of 192 frames. Register bit meaning will depend upon the source
transmission.
User bit 4 contains the state of user bytes 12, 13, 14 and 15 of the
block according to SPDI_CTL.UCBITS_SEL. The SPDI_UBITS
register will always reflect the condition of the current decoded block
of 192 frames. Register bit meaning will depend upon the source
transmission.
User bit 5 contains the state of user bytes 16, 17, 18 and 19 of the
block according to SPDI_CTL.UCBITS_SEL. The SPDI_UBITS
register will always reflect the condition of the current decoded block
of 192 frames. Register bit meaning will depend upon the source
transmission.
User bit 6 contains the state of user bytes 20, 21, 22 and 23 of the
block according to SPDI_CTL.UCBITS_SEL. The SPDI_UBITS
register will always reflect the condition of the current decoded block
of 192 frames. Register bit meaning will depend upon the source
transmission.
UNLOCK active. This flag gets set to logic ‘1’ if the SPDIF Input
receiver is NOT locked onto an incoming stream. Programmers can
use this UNLOCK indication, in conjunction with the LOCK bit, to
determine the state of the receiver or to make a decision to adjust
the oversampling frequency. See the definition of the LOCK bit.
Possible causes of an out-of-lock state are:
The flag can be cleared by a software write to UNLOCK_CLR.
User/Channel bits available. This flag is set if a new set of user data
bits and channel status bits have been written to the SPDI_UBITSx
and SPDI_CBITSx registers. Updated on a block basis.
i) The oversampling frequency is too high or too low with respect
to the applied input SPDIF sample rate.
ii) Too much jitter in SPDIF input stream.
iii) Absent, invalid or corrupted SPDIF stream applied to the
interface/receiver.
PNX15xx/952x Series
Chapter 18: SPDIF Input
© NXP B.V. 2007. All rights reserved.
18-576