GD82559C S L3DF Intel, GD82559C S L3DF Datasheet
GD82559C S L3DF
Specifications of GD82559C S L3DF
Related parts for GD82559C S L3DF
GD82559C S L3DF Summary of contents
Page 1
Fast Ethernet* Multifunction PCI/ CardBus Controller Networking Silicon Product Features Optimum Integration for Lowest Cost Solution — Integrated IEEE 802.3 10BASE-T and 100BASE-TX compatible PHY — Glueless 32-bit PCI master interface — Glueless CardBus master interface — Modem interface ...
Page 2
... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel's website at http://www.intel.com. ...
Page 3
Revision History Revision Revision Date Jan. 1999 1.0 May 1999 2.0 Mar. 2000 2.1 May 2001 2.2 July 2004 2.3 Sept 2004 2.4 Aug 2005 2.5 Datasheet Description First release. • Preliminary 82559 C-step updates: • Added Section 1.3, "Enhancements ...
Page 4
Networking Silicon Note: This page left intentionally blank. iv Datasheet ...
Page 5
Contents 1.0 Introduction......................................................................................................................... 1 1.1 82559 Overview .................................................................................................... 1 1.2 Features, Enhancements, and Changes to the 82559 from the 82558................. 1 1.3 Enhancements to the 82559 C-Step ..................................................................... 2 2.0 82559 Architectural Overview ............................................................................................ 3 2.1 Parallel Subsystem Overview................................................................................ 3 ...
Page 6
Networking Silicon 5.1.1 100BASE-TX Transmit Clock Generation .............................................. 39 5.1.2 100BASE-TX Transmit Blocks ............................................................... 39 5.1.3 100BASE-TX Receive Blocks ................................................................ 42 5.1.4 100BASE-TX Collision Detection ........................................................... 43 5.1.5 100BASE-TX Link Integrity and Auto-Negotiation Solution.................... 43 5.1.6 Auto 10/100 ...
Page 7
Maximum Latency Register ....................................................................63 8.1.18 Capability ID Register.............................................................................63 8.1.19 Next Item Pointer....................................................................................63 8.1.20 Power Management Capabilities Register .............................................63 8.1.21 Power Management Control/Status Register (PMCSR).........................64 8.1.22 Data Register .........................................................................................64 8.2 Function 1: Modem PCI Configuration Space .....................................................66 8.2.1 Modem Configuration ...
Page 8
Networking Silicon 10.1.3 Register 2: PHY Identifier Register Bit Definitions ................................ 87 10.1.4 Register 3: PHY Identifier Register Bit Definitions ................................ 87 10.1.5 Register 4: Auto-Negotiation Advertisement Register Bit Definitions .... 87 10.1.6 Register 5: Auto-Negotiation Link Partner ...
Page 9
... Introduction 1.1 82559 Overview The 82559 is Intel's second generation fully integrated 10BASE-T/100BASE-TX LAN solution. The 82559 consists of both the Media Access Controller (MAC) and the physical layer (PHY) interface combined into a single component solution. The 82559 builds on the basic functionality of the 82558. In addition to the 82558, the 82559 has added new features and enhancements: • ...
Page 10
... Backward compatible software with 82558 and 82557 • TCP/UDP checksum offload capabilities • Support for Intel’s Adaptive Technology The following is a list of changes that were made from the 82558 B-step Fast Ethernet Controller to the 82559 Fast Ethernet Multifunction PCI/CardBusController. • ...
Page 11
Architectural Overview Figure high level block diagram of the 82559 divided into five main subsystems: a parallel subsystem, a FIFO subsystem, the Total Cost of Ownership (TCO) subsystem, the 10/100 Mbps Carrier Sense ...
Page 12
Networking Silicon micromachine during the processing of transmit or receive frames by the 82559. A typical micromachine function is to transfer a data buffer pointer field to the 82559 DMA unit for direct access to the data buffer. ...
Page 13
Mbps Serial CSMA/CD Unit Overview The CSMA/CD unit of the 82559 allows connected to either 100 Mbps Ethernet network. The CSMA/CD unit performs all of the functions of the 802.3 protocol such ...
Page 14
Networking Silicon Note: This page left intentionally blank. 6 Datasheet ...
Page 15
Signal Descriptions 3.1 Signal Type Definitions Type Name IN Input OUT Output T/S Tri-State S/T/S Sustained Tri-State O/D Open Drain A/I Analog Input A/O Analog Output B Bias 3.2 PCI Bus and CardBus Interface Signals 3.2.1 Address and Data ...
Page 16
Networking Silicon 3.2.2 Interface Control Signals Symbol Type FRAME# S/T/S IRDY# S/T/S TRDY# S/T/S STOP# S/T/S IDSEL IN DEVSEL# S/T/S REQ# T/S GNT# IN INTA# O/D SERR# O/D PERR# S/T/S 8 Name and Function Cycle Frame. The cycle ...
Page 17
System and Power Management Signals Symbol Type CLK IN IN/OUT CLKRUN# O/D RST# IN PME# O/D (PCI) CSTSCHG OUT (CardBus)/ WOL (PCI) ISOLATE# IN ALTRST VIO IN Datasheet Name and Function Clock. The Clock signal provides the ...
Page 18
Networking Silicon 3.3 Local Memory Interface Signals Note: All unused Flash Address and Data pins must be left floating. Some of these pins have undocumented test functionality and can cause unpredictable behavior if they are unnecessarily connected to ...
Page 19
Symbol Type FLA[7]/ T/S CLKEN FLA[6:2] OUT FLA[1]/ T/S AUXPWR FLA[0]/ T/S PCIMODE# EECS OUT FLCS#/AEN OUT FLOE# OUT FLWE# OUT CFCS# OUT CFCLK OUT Datasheet Name and Function Flash Address[7]/Clock Enable. This is a multiplexed pin and acts as ...
Page 20
Networking Silicon 3.4 System Management Bus (SMB) Interface Signals Symbol Type IN SMBD O/D IN SMBCLK O/D SMBALRT# O/D 3.5 Testability Port Signals Symbol Type TEST IN TCK TEXEC IN TO OUT 3.6 PHY Signals ...
Page 21
Symbol Type ACTLED# OUT LILED# OUT SPEEDLED# OUT RBIAS100 B RBIAS10 B VREF B a. 649 Ω for RBIAS 100 is only a recommended value and should be fine tuned for various designs. b. 619 Ω for RBIAS 10 is ...
Page 22
Networking Silicon Note: This page left intentionally blank. 14 Datasheet ...
Page 23
Media Access Control Functional Description 4.1 82559 Initialization The 82559 has four sources for initialization. They are listed according to their precedence: 1. ALTRST# Signal 2. PCI RST# Signal 3. Software Reset (Software Command) 4. Selective Reset (Software ...
Page 24
Networking Silicon 4.1.2 Initialization Effects on TCO Functionality The 82559 has the ability to be controlled by two masters, the host CPU on the PCI bus and the TCO controller on the SMB. The 82559 may be initialized ...
Page 25
CPU accesses to the EEPROM through its CSR • CPU accesses to the 82559 PORT address via the CSR • CPU accesses to the MDI control register in the CSR • CPU accesses to the Flash control register in ...
Page 26
Networking Silicon Read Accesses: The CPU, as the initiator, drives address lines AD[31:0], the command and byte enable lines C/BE#[3:0] and the control lines IRDY# and FRAME slave, the 82559 controls the TRDY# signal and provides ...
Page 27
Flash Buffer Accesses The CPU accesses to the Flash buffer are very slow. For this reason the 82559 issues a target- disconnect at the first data access. The 82559 asserts the STOP# signal to indicate a target- disconnect. The ...
Page 28
Networking Silicon Flash buffer. When TRDY# is asserted, the 82559 drives valid data on the AD[31:0] lines. The CPU can also insert wait states by de-asserting IRDY# until it is ready. Flash buffer read accesses can be byte ...
Page 29
Figure 6. PCI Retry Cycle Note: The 82559 is considered the target in the above diagram; thus, TRDY# is not asserted. A Retry may also occur in the following two scenarios: • Card Information Structure (CIS) in memory is accessed ...
Page 30
Networking Silicon 4.2.1.2 82559 Bus Master Operation As a PCI Bus Master, the 82559 initiates memory cycles to fetch data for transmission or deposit received data and for accessing the memory resident control structures. The 82559 performs zero ...
Page 31
Read Accesses: The 82559 performs block transfers from host system memory in order to perform frame transmission on the serial link. In this case, the 82559 initiates zero wait state memory read burst cycles for these accesses. The length of ...
Page 32
Networking Silicon 4.2.1.2.1 Memory Write and Invalidate The 82559 has four Direct Memory Access (DMA) channels. Of these four channels, the Receive DMA is used to deposit the large number of data bytes received from the link into ...
Page 33
When the arbitration counter’s feature is enabled (in other words, the Transmit DMA Maximum Byte Count value is set in the Configure command), the 82559 switches to other pending DMAs on cache line boundary only. Note the following: • ...
Page 34
Networking Silicon 4.2.4 Power Management Event and Card Status Change Signals The 82559 supports power management indications in both the PCI and CardBus mode. In CardBus systems, the CSTSCHG pin is used for power management event indication. The ...
Page 35
D0u is the 82559’s initial power state following a power on reset event and prior to the Base Address Registers (BARs) being accessed. While in the D0u state, the 82559 has PCI slave functionality to support its initialization by the ...
Page 36
Networking Silicon wake-up functionality while the PCI power is off. The typical current consumption of the 82559 is 125 mA at 3.3 V. Thus, a dual power plane is not required. If connected to an auxiliary power source, ...
Page 37
In many systems, the PCI RST# signal is asserted low whenever the PCI bus is inactive. In these systems, the 82559 B-step device and later devices allow the ISOLATE# pin to be driven from the PCI RST# signal. In this ...
Page 38
Networking Silicon The behavior of the PCI RST# signal and the internal 82559 initialization signal are shown in the figure below. PCI RST# Internal hardware reset PCI RST# Internal hardware reset ISOLATE# Internal hardware reset Figure 10. 82559 ...
Page 39
D0u D0a (with power) Dx (x>0 without PME#) 4.3.2 Wake-up Events There are two types of wake-up events: “Interesting” Packets and Link Status Change. These two events are detailed below. Note: The wake-up event is supported ...
Page 40
Networking Silicon When the 82559 is in one of the low power states, it searches for a predefined pattern in the first 128 bytes of the incoming packets. The only exception is the Magic Packet, which is scanned ...
Page 41
When the 82559 is in WOL mode: • The 82559 scans incoming packets for a Magic Packet. When it receives a Magic packet, the 82559 asserts the PME# signal (until cleared) and the CSTSCHG signal for 52 ms. • The ...
Page 42
Networking Silicon All accesses, either read or write, are preceded by a command instruction to the device. The address field is six bits for a 64 register EEPROM or eight bits for a 256 register EEPROM. The end ...
Page 43
The 82559 EEPROM format is shown below in Word Sig 0000b FBH FCH FDH Modem Program Interface (02) FEH Modem Power Dissipation (D0-D3) Figure 12. 82559 EEPROM Format Note that word ...
Page 44
Networking Silicon Table 1. EEPROM Words Field Descriptions Bits Name Word Deep Power AH, 6 Down Word Wake on LAN AH, 5 Word Reserved AH, 4:3 Word AH, 2 Word Standby Enable AH, 1 Word Modem AH, 0 ...
Page 45
Full Duplex When operating in full duplex mode the 82559 can transmit and receive frames simultaneously. Transmission starts regardless of the state of the internal receive path. Reception starts when the internal PHY detects a valid frame on the ...
Page 46
Networking Silicon 4.9 Media Independent Interface (MII) Management Interface The MII management interface allows the CPU to control the PHY unit via a control register in the 82559. This allows the software driver to place the PHY in ...
Page 47
Physical Layer Functional Description 5.1 100BASE-TX PHY Unit 5.1.1 100BASE-TX Transmit Clock Generation A 25 MHz crystal MHz oscillator is used to drive the PHY unit’s X1 and X2 pins. The PHY unit derives its ...
Page 48
Networking Silicon Table 2. 4B/5B Encoder 5.1.2.2 100BASE-TX Scrambler and MLT-3 Encoder Data is scrambled in 100BASE-TX in order to reduce electromagnetic emissions during long transmissions of high-frequency data codes. The scrambler logic accepts 5 bits from the ...
Page 49
When an NRZ “0” arrives at the input of the encoder, the last output level is maintained (either positive, negative or zero). When an NRZ “1” arrives at the input of the encoder, the output steps to the next level. ...
Page 50
Networking Silicon The magnetics module that is external to the PHY unit converts I required by the TP-PMD specification. The same magnetics used for 100BASE-TX mode should also work in 10BASE-T mode. The following is a list of ...
Page 51
Receive Error Detection and Reporting In 100BASE-TX mode, the PHY unit can detect errors in receive data in a number of ways. Any of the following conditions is considered an error: • Link integrity fails in the middle ...
Page 52
Networking Silicon The PHY unit auto-select function determines the operation speed of the media based on the link integrity pulses it receives Fast Link Pulses (FLPs) are detected and Normal Link Pulses (NLPs) are detected, the ...
Page 53
Twisted Pair Ethernet (TPE) Receive Buffer and Filter In 10 Mbps mode, data is expected to be received on the receive differential pair after passing through isolation transformers. The filter is implemented inside the PHY unit for supporting ...
Page 54
Networking Silicon 5.2.7 10BASE-T Full Duplex The PHY unit supports 10 Mbps full duplex by disabling the collision function, the squelch test, and the carrier sense transmit function. This allows the PHY unit to transmit and receive simultaneously, ...
Page 55
Auto-Negotiation or Parallel Detection with no data packets being transmitted. Connection is then established either by FLP exchange or Parallel Detection. The PHY unit will look for both FLPs and link integrity pulses. The following diagram illustrates this ...
Page 56
Networking Silicon Figure 16 provides possible schematic diagrams for configurations using two and three LEDs. 82559ER SpeedLED Figure 16. Two and Three LED Schematic Diagram 48 LILED ACTLED SpeedLED LILED ACTLED VCC VCC Datasheet ...
Page 57
Modem Functionality The local port mimics the standard 8-bit interface of a modem to the host system and emulates a 16550 Universal Asynchronous Receiver/Transceiver (UART) modem interface. The modem interface includes the following: • 8-bit data bus: FLD[7:0] ...
Page 58
Networking Silicon 2. Clear the BD bit in the EEPROM. This enables both the modem and boot ROM. This allows the Boot Enable bit in the Expansion BAR to select which external device (modem or Flash) is active ...
Page 59
TCO Functionality The 82559 supports management communication to reduce Total Cost of Ownership (TCO). It has a System Management Bus (SMB) on which the 82559 is a slave device. The SMB is used as an interface between the ...
Page 60
Networking Silicon The 82559 completes the following process for the during nominal operation of the transmit command in TCO mode. 1. The 82559 completes the current transmit DMA. 2. The 82559 sets the TCO request bit in the ...
Page 61
System Functionality without a TCO Controller This section describes the 82559 functionality when it is connected on the SMB directly to an integrated host controller. Receive Functionality - In the power-up state, the 82559 transfers TCO packets to the ...
Page 62
Networking Silicon • TCO packet received • Low power state change • PHY read 7.3.2 Alert Response Address (ARA) Cycle If a slave device needs to initiate a session, it should assert the SMBALRT signal as follow: SMBALRT# ...
Page 63
PCI and CardBus Configuration Registers The 82559 acts as both a master and a slave on the PCI bus master, the 82559 interacts with the system main memory to access data for transmission or deposit received data. ...
Page 64
Networking Silicon 8.1.2 PCI Command Register The 82559 Command register at word address 04H in the PCI configuration space provides control over the 82559’s ability to generate and respond to PCI cycles 82559 is logically disconnected from the ...
Page 65
PCI Status Register The 82559 Status register is used to record status information for PCI bus related events. The format of this register is shown in the figure below. Detected Parity Error Signaled System Error Received Master Abort Received ...
Page 66
Networking Silicon Table 5. PCI Status Register Bits Bits Name 24 Parity Error Detected 23 Fast Back-to-Back 20 Capabilities List 19:16 Reserved 8.1.4 PCI Revision ID Register The Revision 8-bit read only register with a ...
Page 67
Note: Bit 3 is set to 1b only if the value 00001000b (8H) is written to this register, and bit 4 is set to 1b only if the value of 00010000b (16H) is written to this register. All other bits ...
Page 68
Networking Silicon 31 Reserved I/O space indicator Figure 26. Base Address Register for I/O Mapping Note: Bit 0 in all base registers is read only and used to determine whether the register maps into memory or I/O space. ...
Page 69
LAN/modem combination design, the CFCS# signal will be de-asserted (high) when the Boot Disable bit is not set in the EEPROM and the ROM enable bit is set in the Expansion ROM Base Address Register. After the initial access to ...
Page 70
Networking Silicon The 82559 checks bit numbers 15, 14, and 13 in the EEPROM, word AH and functions according to Table 7 below. Table 7. 82559 ID Fields Programming Signature ID (Bits 15:14) (Bit 13) b 11b , ...
Page 71
Maximum Latency Register The Maximum Latency (Max_Lat) register is an optional read only register for bus masters and is not applicable to non-master devices. This register defines how often a device needs to access the PCI bus. The default ...
Page 72
Networking Silicon 8.1.21 Power Management Control/Status Register (PMCSR) The Power Management Control/Status is a word register used to determine and change the current power state of the 82559 and control the power management interrupts in a ...
Page 73
Table 10. 82559 B-step Ethernet Data Register Data Select Table 11. 82559 C-step Ethernet Data Register Data Select Datasheet Data Scale Power Consumption = 40 (400 mW Power Dissipated = 58 (580 mW) 5 ...
Page 74
Networking Silicon 8.2 Function 1: Modem PCI Configuration Space In PCI systems and CardBus systems, the 82559 supports a dual function device: LAN/modem. The LAN is defined as function zero, and the modem is defined as function one. ...
Page 75
Modem Command Register The Modem Command field bit word register and provides basic control over the modem’s ability to respond to PCI/CardBus accesses. The Command register’s structure is shown in the table below. Table 12. Power ...
Page 76
Networking Silicon 8.2.4 Modem Revision ID Register The Modem Revision ID register is a Dword, read only field composed of the Revision ID byte and a 24-bit Class Code register. Its value is loaded from the ...
Page 77
Modem Subsystem ID Register The Modem Subsystem bit read only register. Its value is loaded from the EEPROM and is a reflection of register 2EH in Function 0, LAN (Ethernet) function. 8.2.11 Modem Capabilities Pointer ...
Page 78
Networking Silicon 8.2.16 Modem Support in PCI Mode The 82559 C-step supports modem interface in PCI mode. The Modem Enable (MDM) bit in the EEPROM can be activated in PCI systems without the loss of BootROM support. In ...
Page 79
Control/Status Registers 9.1 LAN (Ethernet) Control/Status Registers The 82559’s Control/Status Register (CSR) is illustrated in the figure below. D31 Upper Word SCB Command Word EEPROM Control Register PMDR Reserved Figure 28. 82559 Control/Status Register NOTE: In Figure 28 above, ...
Page 80
Networking Silicon MDI Control Register: Receive DMA Byte Count: Flow Control Register: PMDR: General Control: General Status: Function Event: Function Event Mask: Function Present State: Force Event: 72 The MDI Control register allows the CPU to read and ...
Page 81
System Control Block Status Word The System Control Block (SCB) Status Word contains status information relating to the 82559’s Command and Receive units. Bits Name CNA 12 RNR 11 MDI 10 SWI 9 ER ...
Page 82
Networking Silicon 9.1.3 System Control Block General Pointer The System Control Block (SCB) General Pointer is a 32-bit field that points to various data structures depending on the command in the CU Command or RU Command field. 9.1.4 ...
Page 83
Early Receive Interrupt The Early Receive Interrupt register allows the 82559 to generate an early interrupt depending on the length of the frame. An early interrupt is indicated by the ER bit in the SCB Status Word and the ...
Page 84
Networking Silicon 9.1.12 General Control Register The General Control register is a byte register and is described below. The General Control register is used in CardBus mode only. Table 17. General Control Register Bits Default 7:2 000000b 1 ...
Page 85
The 82559 supports only the interrupt and general wake-up event bits in the card status change registers. These registers compliment the PCI Power Management registers in a non-ACPI compliant OS. They are initialized by a power-up reset on the ALTRST# ...
Page 86
Networking Silicon Table 20. LAN Function Event Mask Register Bits Function 4 GWAKE 3 Reserved 2 BVD RDY 1 BVD WP 0 Reserved 9.1.14.3 LAN Function Present State Register The Function Present State register reflects the current state ...
Page 87
LAN Force Event Register The Force Event register simulates status change events for troubleshooting purposes. This register provides the ability to simulate events by forcing values into the Function Event register. Table 22. LAN Force Event Register Bits Function ...
Page 88
Networking Silicon Table 23. 82558 Statistical Counters ID Counter 24 Transmit Single Collisions 28 Transmit Multiple Collisions 32 Transmit Total Collisions 36 Receive Good Frames 40 Receive CRC Errors 44 Receive Alignment Errors 48 Receive Resource Errors 52 ...
Page 89
Table 23. 82558 Statistical Counters ID Counter 72 Flow Control Receive Unsupported 76 Receive TCO Frames 78 Transmit TCO Frames The Statistical Counters are initially set to zero by the 82559 after reset. They cannot be preset to anything other ...
Page 90
Networking Silicon • Modem CIS address space: 100H to 1FFH (loaded from EEPROM) 9.3.2 Modem Base I/O Addressing The modem base I/O addressing is an 8-byte address space. During I/O cycles, accesses to the modem port are byte ...
Page 91
Modem Function Event Mask Register The Modem Function Event Mask register masks CSTSCHG and INTA# assertion as shown in Table 24 below. Table 24. Modem Function Event Mask Register Bits Function 31:16 Reserved 15 INTR 14 WKUP 13:7 Reserved ...
Page 92
Networking Silicon Table 25. Modem Function Present State Register Bits Function 2 BVD RDY 1 BVD WP 0 Reserved 9.3.3.4 Modem Force Event Register The Modem Force Event register simulates status change events for troubleshooting purposes ...
Page 93
PHY Unit Registers The 82559 provides status and accepts management information via the Management Data Interface (MDI) within the CSR space. Acronyms mentioned in the registers are defined as follows: SC: Self cleared. RO: Read only. E: EEPROM setting ...
Page 94
Networking Silicon Bit(s) Name 9 Restart Auto- Negotiation 8 Duplex Mode 7 Collision Test 6:0 Reserved 10.1.2 Register 1: Status Register Bit Definitions Bit(s) Name 15 Reserved 14 100BASE-TX Full Duplex 13 100 Mbps Half Duplex 12 10 ...
Page 95
Register 2: PHY Identifier Register Bit Definitions Bit(s) Name 15:0 PHY ID (high byte) 10.1.4 Register 3: PHY Identifier Register Bit Definitions Bit(s) Name 15:0 PHY ID (low byte) 10.1.5 Register 4: Auto-Negotiation Advertisement Register Bit Definitions Bit(s) Name ...
Page 96
Networking Silicon 10.1.7 Register 6: Auto-Negotiation Expansion Register Bit Definitions Bit(s) Name 15:5 Reserved 4 Parallel Detection Fault 3 Link Partner Next page Able 2 Next Page Able 1 Page Received 0 Link Partner Auto- Negotiation Able 10.2 ...
Page 97
Bit(s) Name 9 10BASE-T Power-Down 8 Polarity 7:2 Reserved 1 Speed 0 Duplex Mode 10.3.2 Register 17: PHY Unit Special Control Bit Definitions Bit(s) Name 15 Scrambler By- pass 14 By-pass 4B/5B 13 Force Transmit H- Pattern 12 Force 34 ...
Page 98
Networking Silicon Bit(s) Name 2 Extended Squelch 1 Link Integrity Disable 0 Jabber Function Disable 10.3.3 Register 18: PHY Address Register Bit(s) Name 15:5 Reserved 4:0 PHY Address 10.3.4 Register 19: 100BASE-TX Receive False Carrier Counter Bit Definitions ...
Page 99
Register 22: Receive Symbol Error Counter Bit Definitions Bit(s) Name 15:0 Symbol Error Counter 10.3.8 Register 23: 100BASE-TX Receive Premature End of Frame Error Counter Bit Definitions Bit(s) Name 15:0 Premature End of Frame 10.3.9 Register 24: 10BASE-T Receive ...
Page 100
Networking Silicon 10.3.12 Register 27: PHY Unit Special Control Bit Definitions Bit(s) Name 15:3 Reserved 2:0 LED Switch Control 92 Description These bits are reserved and should be set to 0b. Value ACTLED LILED 000 Activity Link 001 ...
Page 101
Test Port Functionality 11.1 Introduction The 82559’s NAND Tree Test Access Port (TAP) is the access point for test data to and from the device. The port provides the ability to perform basic production level testing. The port ...
Page 102
Networking Silicon 11.3.2 NAND Tree The NAND Tree test mode is the most useful of the asynchronous test modes. It enables the placement of the 82559 to be validated at board test. The NAND Tree was chosen for ...
Page 103
Table 26. NAND Tree Chains (NAND Tree Output) Datasheet Chain Order Chain 1 (FLOE#) 25 AD15 26 AD14 27 AD13 28 AD12 29 AD11 30 AD10 31 AD9 32 AD8 33 C/BE0# 34 AD7 35 AD6 36 AD5 37 AD4 ...
Page 104
Networking Silicon Note: This page is intentionally left blank. 96 Datasheet ...
Page 105
Electrical and Timing Specifications 12.1 Absolute Maximum Ratings Maximum ratings are listed below: Case Temperature under Bias . . . . . . . . . . . . . . . . . . . . . . ...
Page 106
Networking Silicon Table 28. PCI/CardBus Interface DC Specifications V Output High Voltage OHP V Output Low Voltage OLP C Input Pin Capacitance INP C CLK Pin Capacitance CLKP C IDSEL Pin Capacitance IDSEL L Pin Inductance PINP NOTES: ...
Page 107
Table 31. LED Voltage/Current Characteristics Symbol Parameter V Output High Voltage OHLED V Output Low Voltage OLLED Table 32. 100BASE-TX Voltage/Current Characteristics Symbol Parameter Input Differential R ID100 Impedance Input Differential V IDA100 Accept Peak Voltage Input Differential V IDR100 ...
Page 108
Networking Silicon 12.3 AC Specifications Table 34. AC Specifications for PCI Signaling Symbol Parameter Switching Current High I OH(AC) (Test Point) Switching Current Low I OL(AC) (Test Point) Low Clamp I CL Current High Clamp I CH Current ...
Page 109
Timing Specifications 12.4.1 Clocks Specifications 12.4.1.1 PCI/CardBus Clock Specifications The 82559 uses the PCI Clock signal directly. measurement points for the PCI Clock signal. 0.475V CC 0.4V CC 0.325V CC Figure 29. PCI/CardBus Clock Waveform Table 37. PCI/CardBus Clock ...
Page 110
Networking Silicon 12.4.2 Timing Parameters 12.4.2.1 Measurement and Test Conditions Figure 30, Figure 31, and done. The component test guarantees that all timings are met with minimum clock slew rate (slowest edge) and voltage swing. The design must ...
Page 111
Table 39. Measure and Test Condition Parameters V step V step Input Signal Edge NOTE: Input test is done with 0.1V for testing input timing. 12.4.2.2 PCI/CardBus Timings Table 40. PCI/CardBus Timing Parameters Symbol PCI CLK to Signal Valid Delay ...
Page 112
Networking Silicon 12.4.2.3 Flash/Modem Interface Timings The 82559 is designed to support up to 150 nanoseconds of Flash access time. The V the Flash implementation should be connected permanently Thus, writing to the Flash is ...
Page 113
NOTES: 1. These timing specifications apply to Flash read cycles. The Flash timings referenced are 28F020-150 timings. 2. These timing specifications apply to Flash write cycles. The Flash timings referenced are 28F020-150 timings. FLADDR FLCS# FLOE# FLDATA-R IOCHRDY Figure 32. ...
Page 114
Networking Silicon 12.4.2.4 EEPROM Interface Timings The 82559 is designed to support a standard 64x16 or 256x16 serial EEPROM. the timing parameters for the EEPROM interface signals. The timing parameters are illustrated in Figure 34. Table 42. EEPROM ...
Page 115
PHY Timings Table 43. 10BASE-T NLP Timing Parameters Symbol T56 T NLP Width nlp_wid T57 T NLP Period nlp_per Normal Link Pulse Figure 35. 10BASE-T NLP Timings Table 44. Auto-Negotiation FLP Timing Parameters Symbol T58 T FLP Width (clock/data) ...
Page 116
Networking Silicon Table 45. 100Base-TX Transmitter AC Specification Symbol TDP/TDN Differential T64 T jit Output Peak Jitter 12.4.2.6 SMB Interface Timings Table 46. Flash Timing Parameters Symbol f SMB Operating Frequency smb T84 t Data Hold Time dhs ...
Page 117
... The 82559 is a 196-pin Ball Grid Array (BGA) package. Package dimensions are shown in 37. More information on Intel device packaging is available in the Intel Packaging Handbook, which is available from the Intel Literature Center or your local Intel sales office. Figure 37. Dimension Diagram for the 82559 196-pin BGA Datasheet Networking Silicon — ...
Page 118
Networking Silicon 13.2 Pinout Information 13.2.1 82559 Pin Assignments Table 47. 82559 Pin Assignments Pin A10 A13 B10 B13 C10 C13 D10 D13 ...
Page 119
Table 47. 82559 Pin Assignments Pin G13 H10 H13 J10 J13 K10 K13 L10 L13 M10 FLA15/EESK M13 N10 FLA14/EEDO N13 P1 ...
Page 120
Networking Silicon 13.2.2 82559 Ball Grid Array Diagram SERR# B AD22 AD23 C AD21 RST# D AD18 AD19 E VCCPP VSSPP F IRDY# FRAME# G CLK VIO H STOP# INTA# J PAR PERR# K ...