GD82559C S L3DF Intel, GD82559C S L3DF Datasheet - Page 70

• Manufacturer Part Number: GD82559C S L3DF
• Manufacturer: Intel

Specifications of GD82559C S L3DF

• Lead Free Status / Rohs Status: Not Compliant

82559 — Networking Silicon
8.1.13
8.1.14
8.1.15
8.1.16
62
Table 7.
The 82559 checks bit numbers 15, 14, and 13 in the EEPROM, word AH and functions according
to
82559 ID Fields Programming
a. The Revision ID is subject to change according to the silicon stepping.
b. If bit 15 equals 1b, the EEPROM is invalid and the default values are used.
The above table implies that if the 82559 detects the presence of an EEPROM (as indicated by a
value of 01b in bits 15 and 14), then bit number 13 determines whether the values read from the
EEPROM, words BH and CH, will be loaded into the Subsystem ID (word BH) and Subsystem
Vendor ID (word CH) fields. If bits 15 and 14 equal 01b and bit 13 equals 1b, the three least
significant bits of the Revision ID field are programmed by bits 8-10 of the first EEPROM word,
word AH.
Between the de-assertion of reset and the completion of the automatic EEPROM read, the 82559
does not respond to any PCI configuration cycles. If the 82558 happens to be accessed during this
time, it will Retry the access. More information on Retry is provided in
Premature
Capability Pointer
The Capability Pointer is a hard coded byte register with a value of DCH. It provides an offset
within the Configuration Space for the location of the Power Management registers.
Interrupt Line Register
The Interrupt Line register identifies which system interrupt request line on the interrupt controller
the device’s PCI interrupt request pin (as defined in the Interrupt Pin register) is routed to.
Interrupt Pin Register
The Interrupt Pin register is read only and defines which of the four PCI interrupt request pins,
INTA# through INTD#, a PCI device is connected to. The 82559 is connected the INTA# pin.
Minimum Grant Register
The Minimum Grant (Min_Gnt) register is an optional read only register for bus masters and is not
applicable to non-master devices. It defines the amount of time the bus master wants to retain PCI
bus ownership when it initiates a transaction. The default value of this register for the 82559 is
08H.
11b
00b
01b
01b
01b
(Bits 15:14)
Signature
Table 7
b
, 10b,
below.
Accesses.”
X
1b
0b
0b
(Bit 13)
ID
X
X
1b
0b
(Bit 7)
AltID
1229H
1229H
1229H
1029H
Device
ID
8086H
8086H
8086H
8086H
Vendor
ID
08H
Word AH,
bits 10:8
08H
08H
B-step
Revision ID
09H
Word AH,
bits 10:8
09H
09H
C-step
a
Section 4.2.1.1.3, “Retry
0000H
Word BH
Word BH
Word BH
Subsystem
ID
0000H
Word CH
Word CH
Word CH
Subsystem
Datasheet
Vendor ID