GD82559C S L3DF Intel, GD82559C S L3DF Datasheet - Page 62

• Manufacturer Part Number: GD82559C S L3DF
• Manufacturer: Intel

Specifications of GD82559C S L3DF

• Lead Free Status / Rohs Status: Not Compliant

82559 — Networking Silicon
7.3.2
54
Figure 20. Slave Request for Data Transfer
Alert Response Address (ARA) Cycle
If a slave device needs to initiate a session, it should assert the SMBALRT signal as follow:
If the 82559 is not ready, it indicates this in one of two ways:
1. If the 82559’s PHY unit is in a low power state, the 82559 will not produce the acknowledge
2. If the 82559’s PHY unit is in nominal mode, the 82559 will pull-down the SMBCLK until it is
SMBALRT#
SMBCLK
SMBD
•
•
•
TCO packet received
Low power state change
PHY read
bit after its address appears on the bus. This forces the TCO controller to stop the session and
restart it.
ready. If the 82559 forces the SMBCLK for more then 25 ms, the TCO controller should stop
the transmission and restart it.
The SMBALRT# will rise only if an address match exists.
start
MSB
1
ACK
MSB
1
ACK
stop
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