GD82559C S L3DF Intel, GD82559C S L3DF Datasheet - Page 46

• Manufacturer Part Number: GD82559C S L3DF
• Manufacturer: Intel

Specifications of GD82559C S L3DF

• Lead Free Status / Rohs Status: Not Compliant

82559 — Networking Silicon
4.9
38
Media Independent Interface (MII) Management Interface
The MII management interface allows the CPU to control the PHY unit via a control register in the
82559. This allows the software driver to place the PHY in specific modes such as full duplex,
loopback, power down, etc., without the need for specific hardware pins to select the desired mode.
This structure allows the 82559 to query the PHY unit for status of the link. This register is the
MDI Control Register and resides at offset 10H in the 82559 CSR. (The MDI registers are
described in detail in
to this register and the 82559 reads or writes the control/status parameters to the PHY unit through
the MDI register. Although the82559 follows the MII format, the MI bus is not accessible on
external pins.
Section 10.0, “PHY Unit Registers” on page
85.) The CPU writes commands
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