GD82559C S L3DF Intel, GD82559C S L3DF Datasheet - Page 27

• Manufacturer Part Number: GD82559C S L3DF
• Manufacturer: Intel

Specifications of GD82559C S L3DF

• Lead Free Status / Rohs Status: Not Compliant

Datasheet
Figure 4. Flash Buffer Read Cycle
4.2.1.1.2 Flash Buffer Accesses
The CPU accesses to the Flash buffer are very slow. For this reason the 82559 issues a target-
disconnect at the first data access. The 82559 asserts the STOP# signal to indicate a target-
disconnect. The figures below illustrate memory CPU read and write accesses to the 128 Kbyte
Flash buffer. The longest burst cycle to the Flash buffer contains one data access only.
Read Accesses: The CPU, as the initiator, drives the address lines AD[31:0], the command and
byte enable lines C/BE#[3:0] and the control lines IRDY# and FRAME#. The 82559 controls the
TRDY# signal and de-asserts it for a certain number of clocks until valid data can be read from the
CLK
FRAME#
AD
C/BE#
IRDY#
TRDY#
DEVSEL#
STOP#
MEM RD
ADDR
BE#
Networking Silicon — 82559
DATA
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