GD82559C S L3DF Intel, GD82559C S L3DF Datasheet - Page 11

• Manufacturer Part Number: GD82559C S L3DF
• Manufacturer: Intel

Specifications of GD82559C S L3DF

• Lead Free Status / Rohs Status: Not Compliant

2.0
2.1
Datasheet
Figure 1. 82559 Block Diagram
82559 Architectural Overview
Figure 1
parallel subsystem, a FIFO subsystem, the Total Cost of Ownership (TCO) subsystem, the 10/100
Mbps Carrier Sense Multiple Access with Collision Detect (CSMA/CD) unit, and the 10/100 Mbps
physical layer (PHY) unit.
Parallel Subsystem Overview
The parallel subsystem is broken down into several functional blocks: a PCI bus master interface, a
micromachine processing unit and its corresponding microcode ROM, and a PCI Target Control/
Flash/EEPROM/Modem interface. The parallel subsystem also interfaces to the FIFO subsystem,
passing data (such as transmit, receive, and configuration data) and command and status
parameters between these two blocks.
The dual function LAN and modem interface provides a complete glueless connection to the PCI
bus and is compliant with the PCI Bus Specification, Revision 2.2. The 82559 provides 32 bits of
addressing and data, as well as the complete control interface to operate on a PCI bus. As a PCI
target, it follows the PCI configuration format which allows all accesses to the 82559 to be
automatically mapped into free memory and I/O space upon initialization of a PCI system. For
processing of transmit and receive frames, the 82559 operates as a master on the PCI bus, initiating
zero wait state transfers for accessing these data parameters.
The 82559 Control/Status Register Block is part of the PCI target element. The Control/Status
Register block consists of the following 82559 internal control registers: System Control Block
(SCB), PORT, Flash Control, EEPROM Control, Modem Control and Management Data Interface
(MDI) Control.
The micromachine is an embedded processing unit contained in the 82559 that enables Adaptive
Technology. The micromachine accesses the 82559 microcode ROM working its way through the
operation codes, opcodes (or instructions), contained in the ROM to perform its functions.
Parameters accessed from memory such as pointers to data buffers are also used by the
CardBus
Interface
PCI/
is a high level block diagram of the 82559. It is divided into five main subsystems: a
Flash/Modem/EEPROM
Data Interface Unit
Addressing Unit -
Four Channel
Interface Unit
Modem Interface
PCI Target and
Local Memory/
PCI Bus
Interface
(DIU)
(BIU)
DMA
machine
Ported
Micro-
Interface
Interface
FIFO
Dual
SMB
SMB
FIFO Control
Tx FIFO
Rx FIFO
3 Kbyte
3 Kbyte
10/100 Mbps
CSMA/CD
Networking Silicon — 82559
100BASE-TX/
10BASE-T
PHY
Interface
TPE
3