GD82559C S L3DF Intel, GD82559C S L3DF Datasheet - Page 71

• Manufacturer Part Number: GD82559C S L3DF
• Manufacturer: Intel

Specifications of GD82559C S L3DF

• Lead Free Status / Rohs Status: Not Compliant

8.1.17
8.1.18
8.1.19
8.1.20
Datasheet
Table 8. Power Management Capability Register
Maximum Latency Register
The Maximum Latency (Max_Lat) register is an optional read only register for bus masters and is
not applicable to non-master devices. This register defines how often a device needs to access the
PCI bus. The default value of this register for the 82559 is 18H.
Capability ID Register
The Capability ID is a byte register. It signifies whether the current item in the linked list is the
register defined for PCI power management. PCI power management has been assigned the value
of 02H. The 82559 is fully compliant with the PCI Power Management Specification, Revision 2.2.
Next Item Pointer
The Next Item Pointer is a byte register. It describes the location of the next item in the 82559’s
capability list. Since power management is the last item in the list, this register is set to 0b.
Power Management Capabilities Register
The Power Management Capabilities register is a word read only register. It provides information
on the capabilities of the 82559 related to power management. The 82559 reports a value of FE21H
if it is connected to an auxiliary power source and 7E21H otherwise. It indicates that the 82559
supports wake-up in the D3 state if power is supplied, either V
31:27
26
25
24:22
21
20
19
18:16
Bits
00011b
(no V
11111b
(V
1b
1b
000b
1b
0b (PCI)
1b
(CardBus)
0b
010b
Default
AUX
AUX
)
)
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read/Write
PME Support. This five bit field indicates the power states in which
the 82559 may assert PME#. The 82559 supports wake-up in all
power states if it is fed by an auxiliary power supply (V
D1, D2, and D3
D2 Support. If this bit is set, the 82559 supports the D2 power state.
D1 Support. If this bit is set, the 82559 supports the D1 power state.
Auxiliary Current. This field reports whether the 82559 implements
the Data registers. The auxiliary power consumption is the same as
the current consumption reported in the D3 state in the Data register.
Device Specific Initialization (DSI). The DSI bit indicates whether
special initialization of this function is required (beyond the standard
PCI configuration header) before the generic class device driver is
able to use it. DSI is required for the 82559 after D3-to-D0 reset.
Reserved (PCI)/Auxiliary Power Source (CardBus). When this bit
is set to ‘1’, it indicates that the 82559 requires auxiliary power
supplied by the system for wake-up from the D3
PME Clock. The 82559 does not require a clock to generate a power
management event.
Version. A value of 010b indicates that the 82559 complies with of
the PCI Power Management Specification, Revision 2.2.
hot
if it is fed by PCI power.
Description
cc
or V
Networking Silicon — 82559
AUX
.
cold
state.
AUX
) and D0,
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