GD82559C S L3DF Intel, GD82559C S L3DF Datasheet - Page 83

• Manufacturer Part Number: GD82559C S L3DF
• Manufacturer: Intel

Specifications of GD82559C S L3DF

• Lead Free Status / Rohs Status: Not Compliant

9.1.9
9.1.10
9.1.11
Datasheet
Table 16. Power Management Driver Register
Note: The PMDR is initialized at ALTRST# reset only.
Early Receive Interrupt
The Early Receive Interrupt register allows the 82559 to generate an early interrupt depending on
the length of the frame. An early interrupt is indicated by the ER bit in the SCB Status Word and
the assertion of the INTA# signal.
Flow Control Register
The Flow Control Register contains the following fields:
Power Management Driver Register
The 82559 provides an indication in memory and I/O space that a wake-up event has occurred. It is
located in the Power Management Driver (PMDR). The PMDR is used for CardBus mode only.
31
30
29
28:26
25
24
•
•
Bits
Flow Control Command
The Flow Control Command field describes the action of the flow control process (for
example, pause, on, or off).
Flow Control Threshold
The Flow Control Threshold field contains the threshold value (in other words, the number of
free bytes in the Receive FIFO).
0b
0b
0b
000b
0b
0b
Default
Read/Clear
Read/Clear
Read/Clear
Read Only
Read/Clear
Read/Clear
Read/Write
Link Status Change Indication. The link status change bit is set
following a change in link status and is cleared by writing a 1b to it.
Magic Packet. This bit is set when a Magic Packet is received
regardless of the Magic Packet wake-up disable bit in the configuration
command and the PME Enable bit in the Power Management Control/
Status Register. This bit is cleared by writing 1b to it.
Interesting Packet. This bit is set when an “interesting” packet is
received. Interesting packets are defined by the 82559 packet filters.
This bit is cleared by writing 1b to it.
Reserved. These bits are reserved and should be set to 000b.
TCO Request. This bit is set to 1b when the 82559 is busy with TCO
activity.
PME Status. This bit is a reflection of the PME Status bit in the Power
Management Control/Status Register (PMCSR). It is set upon a wake-
up event and is independent of the PME Enable bit.
This bit is cleared by writing 1b to it. This also clears the PME Status
bit in the PMCSR and de-asserts the PME signal. In a CardBus
system, if 1b is written to this field, the General Wake-up (GWAKE) bit
in the Function Event register is cleared.
Description
Networking Silicon — 82559
75