GD82559C S L3DF Intel, GD82559C S L3DF Datasheet - Page 75

• Manufacturer Part Number: GD82559C S L3DF
• Manufacturer: Intel

Specifications of GD82559C S L3DF

• Lead Free Status / Rohs Status: Not Compliant

8.2.2
8.2.3
Datasheet
Table 12. Power Management Control and Status Register
Table 13. Modem Status Register
Modem Command Register
The Modem Command field is a 16 bit word register and provides basic control over the modem’s
ability to respond to PCI/CardBus accesses. The Command register’s structure is shown in the table
below.
Modem Status Register
The Modem Status field is a 16 bit word register. It provides basic track of CardBus related events.
All bits are cleared by PCI RST#.
15:10
9
8
7
6
5
4
3
2
1
0
15
14
13:11
10:9
8
7
6:5
4
3:0
Bits
Bits
000000b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0
0
000
01
0
0
00
1
0000
Default
Default
Read Only
Read Only
Read/Write
Read Only
Read/Write
Read Only
Read Only
Read Only
Read Only
Read/Write
Read/Write
Read/Write
Read/Write
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read/Write
Read/Write
Reserved. These bits are reserved and should be set to 000000b.
Fast Back-to-Back.
System Error Enable.
Wait Cycle Enable.
Parity Error Enable.
VGA (define).
Memory Write and Invalidate.
Special Cycle.
Master Enable.
Memory Access Enable.
I/O Access Enable.
Parity Error.
System Error Enable.
Signaled/Received Target Abort.
Device Select Timing.
Data Parity Detect.
Fast Back-to-Back Capable.
Reserved. These bits are reserved and should be set to 00b.
New Capability.
Reserved. These bits are reserved and should be set to 0000b.
Description
Description
Networking Silicon — 82559
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