GD82559C S L3DF Intel, GD82559C S L3DF Datasheet - Page 81

• Manufacturer Part Number: GD82559C S L3DF
• Manufacturer: Intel

Specifications of GD82559C S L3DF

• Lead Free Status / Rohs Status: Not Compliant

9.1.1
9.1.2
Datasheet
System Control Block Status Word
The System Control Block (SCB) Status Word contains status information relating to the 82559’s
Command and Receive units.
System Control Block Command Word
Commands for the 82559’s Command and Receive units are placed in this register by the CPU.
15
14
13
12
11
10
9
8
7:6
5:2
1:0
31:26
25
24
23:20
19
18:16
Bits
Bits
CX
FR
CNA
RNR
MDI
SWI
ER
FCP
CUS
RUS
Reserved
Specific
Interrupt Mask
SI
M
CUC
Reserved
RUC
Name
Name
Command Unit (CU) Executed. The CX bit indicates that the CU has
completed executing a command with its interrupt bit set.
Frame Received. The FR bit indicates that the Receive Unit (RU) has
finished receiving a frame.
CU Not Active. The CNA bit is set when the CU is no longer active and in
either an idle or suspended state.
Receive Not Ready. The RNR bit is set when the RU is not in the ready
state. This may be caused by an RU Abort command, a no resources
situation, or set suspend bit due to a filled Receive Frame Descriptor.
Management Data Interrupt. The MDI bit is set when a Management Data
Interface read or write cycle has completed. The management data interrupt
is enabled through the interrupt enable bit (bit 29 in the Management Data
Interface Control register in the CSR).
Software Interrupt. The SWI bit is set when software generates an
interrupt.
Early Receive. The ER bit is used for early receive interrupts.
Flow Control Pause. The FCP bit is used as the flow control pause bit.
Command Unit Status. The CUS field contains the status of the Command
Unit.
Receive Unit Status. The RUS field contains the status of the Receive Unit.
These bits are reserved and should be set to 00b.
Specific Interrupt Mask. Setting this bit to 1b causes the 82559 to stop
generating an interrupt (in other words, de-assert the INTA# signal) on the
corresponding event.
Software Generated Interrupt. Setting this bit to 1b causes the 82559 to
generate an interrupt. Writing a 0b to this bit has no effect.
Interrupt Mask. If the Interrupt Mask bit is set to 1b, the 82559 will not
assert its INTA# pin. The M bit has higher precedence that the Specific
Interrupt Mask bits and the SI bit.
Command Unit Command. This field contains the CU command.
This bit is reserved and should be set to 0b.
Receive Unit Command. This field contains the RU command.
Description
Description
Networking Silicon — 82559
73