GD82559C S L3DF Intel, GD82559C S L3DF Datasheet - Page 41

• Manufacturer Part Number: GD82559C S L3DF
• Manufacturer: Intel

Specifications of GD82559C S L3DF

• Lead Free Status / Rohs Status: Not Compliant

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4.7
Datasheet
Note: Flash accesses must always be assembled or disassembled by the 82559 whenever the access is
When the 82559 is in WOL mode:
The 82559 switches from WOL mode to the D0a power state following a setup of the Memory or
I/O Base Address Registers in the PCI Configuration space. While the 82559 is in the D0u, D1, D2,
or D3 power state, if the 82559 receives a Magic packet, it issues a positive pulse for approximately
52 ms on the CSTSCHG pin. For PCI systems and in designs that support the 3-pin header
standard, the CSTSCHG pin acts as the WOL signal.
Parallel Flash/Modem Interface
The 82559’s parallel interface is used for Flash interface only or modem interface only. The 82559
supports a glueless interface to an 8-bit wide, 128 Kbyte, parallel memory device. The parallel
local port is multiplexed with a modem interface in a LAN/modem combination card.
The Flash (or boot PROM) is read from or written to whenever the host CPU performs a read or a
write operation to a memory location that is within the Flash mapping window. All accesses to the
Flash, except read accesses, require the appropriate command sequence for the device used. (Refer
to the specific Flash data sheet for more details on reading from or writing to the Flash device.) The
accesses to the Flash are based on a direct decode of CPU accesses to a memory window defined in
either the 82559 Flash Base Address Register (PCI Configuration space at offset 18H) or the
Expansion ROM Base Address Register (PCI Configuration space at offset 30H). The 82559
asserts control to the Flash when it decodes a valid access.
The 82559 supports an external Flash memory (or boot PROM) of up to 128 Kbyte. The Expansion
ROM address can be separately disabled by setting the corresponding bit in the EEPROM, word
AH.
greater than a byte-wide access. Due to slow access times to a typical Flash and to avoid violating
PCI bus holding specifications (no more than 16 wait states inserted for any cycles that are not
system initiation cycles), the maximum data size is either one word or one byte for a read operation
and one byte only for a write operation.
Serial EEPROM Interface
The serial EEPROM stores configuration data for the 82559 and is a serial in/serial out device. The
82559 supports a either a 64 register or 256 register size EEPROM and automatically detects the
EEPROM’s size. A 256 word EEPROM device is required for a Cardbus system and contains the
CIS information. A 256 word EEPROM device is also required for a TCO enabled system in order
to hold the heartbeat packet. The EEPROM should operate at a frequency of at least 1 MHz.
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The 82559 scans incoming packets for a Magic Packet. When it receives a Magic packet, the
82559 asserts the PME# signal (until cleared) and the CSTSCHG signal for 52 ms.
The Activity LED changes its functionality to indicates that the received frame passed
Individual Address (IA) filtering or broadcast filtering.
The PCI Configuration registers are accessible to the host.
Software should not attempt to access the Flash.
Networking Silicon — 82559
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