GD82559C S L3DF Intel, GD82559C S L3DF Datasheet - Page 101

• Manufacturer Part Number: GD82559C S L3DF
• Manufacturer: Intel

Specifications of GD82559C S L3DF

• Lead Free Status / Rohs Status: Not Compliant

11.0
11.1
11.2
11.3
11.3.1
Datasheet
82559 Test Port Functionality
Introduction
The 82559’s NAND Tree Test Access Port (TAP) is the access point for test data to and from the
device. The port provides the ability to perform basic production level testing. The port provides
two functions:
Asynchronous Test Mode
Four asynchronous test modes are supported for system level design use. The modes are selected
through the use of the test port input pin in static combinations. The test port pins are Test Port
(TEST), Test Port Data Input (TI), Test Port Execute Enable (TEXEC) and Test Port Clock (TCK).
During normal operation the TEST pin must be pulled down through a resistor (pulling TEST high
enables the test mode). All other port inputs may have a pull-down at the designers discretion.
Test Function Description
The 82559 TAP mode supports several tests that can be used in board level design. These tests help
verify basic functionality as well as test the integrity of solder connection on the board. The tests
are described in the following subsections.
Tristate
The tristate command sets all 82559 input and output pins into a tristate (high-Z) mode (all internal
pull-ups and pull-downs are disabled). This mode is entered by setting the following test pin
combination and resetting the device:
•
•
The synchronous IC validation mode is used in the production of the device. This mode gives
the signals their names (for example, Testability Port Clock [TCK]).
The 82559 also supports asynchronous testing modes. These test modes support the validation
of connections at the board level.
TEST = 1
TCK = 0
TEXEC = 0
TI = 1
Networking Silicon — 82559
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