GD82559C S L3DF Intel, GD82559C S L3DF Datasheet - Page 40

• Manufacturer Part Number: GD82559C S L3DF
• Manufacturer: Intel

Specifications of GD82559C S L3DF

• Lead Free Status / Rohs Status: Not Compliant

82559 — Networking Silicon
4.3.2.2
4.4
4.5
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When the 82559 is in one of the low power states, it searches for a predefined pattern in the first
128 bytes of the incoming packets. The only exception is the Magic Packet, which is scanned for
the entire frame. The 82559 will classify the incoming packets as one of the following categories:
Link Status Change Event
The 82559 link status indication circuit is capable of issuing a PME on a link status change from a
valid link to an invalid link condition or vice versa. The 82559 reports a PME link status event in all
power states. The PME# signal is gated by the PME Enable bit in the PMCSR and the CSMA
Configure command.
CardBus Power Management
The CardBus Power Management Proposal differs from the PCI Power Management Specification
in the following manner:
In addition, the 82559 also meets the CardBus requirement for current consumption less than 70
mA in the D0u state.
Wake on LAN (Preboot Wake-up)
When the 82559 is drawing power from an auxiliary power source (V
preboot Wake on LAN (WOL) capabilities as the 82558 device. The 82559 enters WOL mode after
the following events occur:
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No Match. The 82559 discards the packet and continues to process the incoming packets.
TCO Packet. The 82559 implements perfect filtering of TCO packets. After a TCO packet is
processed, the 82559 is ready for the next incoming packet. There are two possible system
environments:
Wake-up Packet. The 82559 is capable of recognizing and storing the first 128 bytes of a
wake-up packet. If a wake-up packet is larger than 128 bytes, its tail is discarded by the 82559.
After the system is fully powered-up, software has the ability to determine the cause of the
wake-up event via the PMDR and dump the stored data to the host memory.
Magic Packets are an exception. The magic packets may cause a power management event and
set an indication bit in the PMDR; however, it is not stored by the 82559 for use by the system
when it is woken up.
The PME# signal is replaced by CSTSCHG which is an active high output signal.
An auxiliary power source, V
An auxiliary power source bit in the PMC register must be set.
The PCI clock signal and the PCI reset signal are guaranteed to be kept low in the B3 state.
An ALTRST# is completed.
The 82559 reads the EEPROM and the WOL bit is set.
— TCO controller on the SMB. The entire TCO packet is transferred to the TCO controller.
— System without TCO controller. TCO packets are treated as any other wake-up packet
and may assert the PME# signal if configured to do so.
AUX
, is supplied on the same V
cc
pins.
AUX
), it can support the same
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