GD82559C S L3DF Intel, GD82559C S L3DF Datasheet - Page 96

• Manufacturer Part Number: GD82559C S L3DF
• Manufacturer: Intel

Specifications of GD82559C S L3DF

• Lead Free Status / Rohs Status: Not Compliant

82559 — Networking Silicon
10.1.7
10.2
10.3
10.3.1
88
Register 6: Auto-Negotiation Expansion Register Bit Definitions
MDI Registers 8 - 15
Registers eight through fifteen are reserved for IEEE.
MDI Register 16 - 31
Register 16: PHY Unit Status and Control Register Bit Definitions
15:5
4
3
2
1
0
15:14
13
12
11
10
Bit(s)
Bit(s)
Reserved
Parallel Detection
Fault
Link Partner Next
page Able
Next Page Able
Page Received
Link Partner Auto-
Negotiation Able
Reserved
Carrier Sense
Disconnect
Control
Transmit Flow
Control Disable
Receive De-
Serializer In-Sync
Indication
100BASE-TX
Power-Down
Name
Name
These bits are reserved and should be set to 0b.
1 = Fault detected via parallel detection (multiple link
fault occurred)
0 = No fault detected via parallel detection
This bit will self-clear on read
1 = Link Partner is Next Page able
0 = Link Partner is not Next Page able
1 = Local drive is Next Page able
0 = Local drive is not Next Page able
1 = New Page received
0 = New Page not received
This bit will self-clear on read.
1 = Link Partner is Auto-Negotiation able
0 = Link Partner is not Auto-Negotiation able
These bits are reserved and should be set to 00b
This bit enables the disconnect function.
1 = Disconnect function enabled
0 = Disconnect function disabled
This bit enables Transmit Flow Control
1 = Transmit Flow Control enabled
0 = Transmit Flow Control disabled
This bit indicates status of the 100BASE-TX Receive
De-Serializer In-Sync.
This bit indicates the power state of 100BASE-TX
PHY unit.
1 = Power-Down
0 = Normal operation
Description
Description
Default
Default
00
--
0
0
0
0
0
0
0
0
1
Datasheet
RO
RO
SC
LH
RO
RO
RO
SC
LH
RO
RW
RW
RW
RO
RO
R/W
R/W