GD82559C S L3DF Intel, GD82559C S L3DF Datasheet - Page 84

• Manufacturer Part Number: GD82559C S L3DF
• Manufacturer: Intel

Specifications of GD82559C S L3DF

• Lead Free Status / Rohs Status: Not Compliant

82559 — Networking Silicon
9.1.12
9.1.13
9.1.14
76
Table 17. General Control Register
Table 18. General Status Register
General Control Register
The General Control register is a byte register and is described below. The General Control register
is used in CardBus mode only.
General Status Register
The General Status register is used in CardBus mode only and is a byte register which indicates the
link status of the 82559.
Ethernet Card Status Change Registers
The PME signal used in PCI systems is replaced by the Card Status Change (CSTSCHG) signal in
CardBus systems. The CardBus specification requires the use of control/status registers related to
CSTSCHG. There are four event related registers.
These CardBus registers are used by software to determine which event has occurred, manage the
event, and control the CSTSCHG signal.
7:2
1
0
7:3
2
1
0
•
•
•
•
Bits
Bits
Function Event Register: Specifies the event that changed status
Function Event Mask Register: Masks CSTSCHG signal assertion for specified events
Function Present State Register: Reflects the current state of each condition that may cause a
status change or interrupt
Force Event Register: Simulates status change events for troubleshooting purposes
000000b
0b
0b
00000b
--
--
0b
Default
Default
Read Only
Read/Write
Read/Write
Read Only
Read Only
Read Only
Read Only
Read/Write
Read/Write
Reserved. These bits are reserved and should be set to 000000b.
Deep Power-Down on Link Down Enable. If a 1b is written to this
field, the 82559 may enter a deep power-down state (sub-3 mA) in the
D2 and D3 power states while the link is down.
In this state, the 82559 does not keep link integrity. This state is not
supported for point-to-point connection of two end stations.
Clockrun Signal Disable. If this bit is set to 1b, then the 82559 will
always request the PCI clock signal. This mode can be used to
overcome potential receive overruns caused by Clockrun signal
latencies over 5 µs.
Reserved. These bits are reserved and should be set to 00000b.
Duplex Mode. This bit indicates the wire duplex mode: full duplex (1b)
or half duplex (0b).
Speed. This bit indicates the wire speed: 100 Mbps (1b) or 10 Mbps
(0b).
Link Status Indication. This bit indicates the status of the link: valid
(1b) or invalid (0b).
Description
Description
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