GD82559C S L3DF Intel, GD82559C S L3DF Datasheet - Page 61

• Manufacturer Part Number: GD82559C S L3DF
• Manufacturer: Intel

Specifications of GD82559C S L3DF

• Lead Free Status / Rohs Status: Not Compliant

7.2
7.3
7.3.1
Datasheet
Figure 19. SMB Session
Note: On the SMB, the send heartbeat packet command is not normally used in the D0 power state. The
System Functionality without a TCO Controller
This section describes the 82559 functionality when it is connected on the SMB directly to an
integrated host controller.
Receive Functionality - In the power-up state, the 82559 transfers TCO packets to the host as any
other packet. These packets include a new status indication bit in the 82559’s Receive Frame
Descriptor (RFD) status and have a specific port number indicating TCO packet recognition. In the
power-down state, the TCO packets are treated as a wake-up packets. The 82559 asserts the PME#
signal and delivers the first 120 bytes of the packet to the host.
Transmit Functionality - The 82559 supports the Heartbeat (HB) transmission command from the
SMB interface. The send HB packet command includes a system health status issued by the
integrated system controller. The 82559 computes a matched checksum and CRC and will
transmit the HB packet from its serial EEPROM. The HB packet size and structure are not limited
as long as it fits within the EEPROM size. In this case, the EEPROM size is 256 words to enable
the storage of the HB packet (the first 64 words are used for driver specific data).
one exception in which it is used in the D0 state is when the system is hung. In normal operating
mode, the heartbeat packets are transmitted through the 82559’s software similar to other packets.
TCO Interface
Support for a TCO controller is through a dedicated SMB interface. The 82559 acts as a slave on
the SMB and supports data (SMBD), clock (SMBCLK), and alert (SMBALRT#) signals. The
82559 meets the 100 KHz SMB requirements according to the specification. It is also functional
with an increased clock frequency of up to 1 MHz and still meets all required SMB timings. A
basic SMB wave form diagram is shown in
SMB Alert Signal (SMBALRT#)
The 82559 operates in slave mode on the SMB during both read and write cycles. When the 82559
transmits data on the SMB (receive packet), it issues the SMBALRT# signal. In response to the
SMBALRT# activation, the host processes the interrupt. It accesses all SMB devices
simultaneously by an Alert Response Address (ARA) cycle. The device(s) that issued the
SMBALRT# signal acknowledges the cycle. If more than one device issued the SMBALRT#, the
highest priority (lowest address) device will win communication. Only the winning device can de-
asserts its SMBALRT# signal.
As a slave device, the 82559 signals the external TCO Controller using SMBALRT#. The
SMBALRT# signal is activated for the following events:
SMBCLK
SMBD
start
MSB
ADDR
R/W#
Figure
ACK
19.
CMD
ACK
Networking Silicon — 82559
BC
ACK
DATA
ACK
stop
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