GD82559C S L3DF Intel, GD82559C S L3DF Datasheet - Page 87

• Manufacturer Part Number: GD82559C S L3DF
• Manufacturer: Intel

Specifications of GD82559C S L3DF

• Lead Free Status / Rohs Status: Not Compliant

9.1.14.4
9.2
Datasheet
Table 22. LAN Force Event Register
Table 23. 82558 Statistical Counters
LAN Force Event Register
The Force Event register simulates status change events for troubleshooting purposes. This register
provides the ability to simulate events by forcing values into the Function Event register.
Statistical Counters
The 82559 provides information for network management statistics by providing on-chip statistical
counters that count a variety of events associated with both transmit and receive. The counters are
updated by the 82559 when it completes the processing of a frame (that is, when it has completed
transmitting a frame on the link or when it has completed receiving a frame). The Statistical
Counters are reported to the software on demand by issuing the Dump Statistical Counters
command or Dump and Reset Statistical Counters command in the SCB Command Unit Command
(CUC) field.
31:16
15
14:5
4
3:0
12
16
20
ID
Bits
0
4
8
Transmit Good Frames
Transmit Maximum Collisions
(MAXCOL) Errors
Transmit Late Collisions (LATECOL)
Errors
Transmit Underrun Errors
Transmit Lost Carrier Sense (CRS)
Transmit Deferred
Reserved
INTR
Reserved
GWAKE
Reserved
Function
Counter
0
0
0
0
0
Default
Bits [31:16] are reserved in the CardBus Specification.
This bit is used for interrupts. Writing 1b in this field will set the interrupt
bit in the LAN Function Event register. If the INTA# pin is not masked,
then it will also be activated. Writing 0b has no effect.
Bits [14:5] are reserved in the CardBus Specification.
This bit is used for general wake-up. Writing 1b in this field will set the
CSTSCHG bit in the LAN Function Event register. If the CSTSCHG pin
is not masked, then it will also be activated. Writing 0b has no effect.
Bits [3:0] are reserved in the CardBus Specification.
This counter contains the number of frames that were
transmitted properly on the link. It is updated only after the
actual transmission on the link is completed, not when the
frame was read from memory as is done for the Transmit
Command Block status.
This counter contains the number of frames that were not
transmitted because they encountered the configured
maximum number of collisions.
This counter contains the number of frames that were not
transmitted since they encountered a collision later than the
configured slot time.
A transmit underrun occurs because the system bus cannot
keep up with the transmission. This counter contains the
number of frames that were either not transmitted or
retransmitted due to a transmit DMA underrun. If the 82559 is
configured to retransmit on underrun, this counter may be
updated multiple times for a single frame.
This counter contains the number of frames that were
transmitted by the 82559 despite the fact that it detected the
de-assertion of CRS during the transmission.
This counter contains the number of frames that were deferred
before transmission due to activity on the link.
Description
Description
Networking Silicon — 82559
79