GD82559C S L3DF Intel, GD82559C S L3DF Datasheet - Page 65
GD82559C S L3DF
Manufacturer Part Number
GD82559C S L3DF
Description
Manufacturer
Intel
Datasheet
1.GD82559C_S_L3DF.pdf
(120 pages)
Specifications of GD82559C S L3DF
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8.1.3
Datasheet
Figure 23. PCI Status Register
Table 5. PCI Status Register Bits
PCI Status Register
The 82559 Status register is used to record status information for PCI bus related events. The
format of this register is shown in the figure below.
Note that bits 21, 22, 26, and 27 are set to 0b and bits 20, 23, and 25 are set to 1b. The PCI Status
register bits are described in the table below.
31
30
29
28
27
26:25
Bits
Detected Parity Error
Signaled System Error
Received Master
Abort
Received Target Abort
Signaled Target Abort
DEVSEL# Timing
Detected Parity Error
Signaled System Error
Received Master Abort
Received Target Abort
Signaled Target Abort
Devsel Timing
Parity Error Detected
Fast Back To Back (target)
Capabilities List
Name
31
This bit indicates whether a parity error is detected. This bit must be
asserted by the device when it detects a parity error, even if parity error
handling is disabled (as controlled by the Parity Error Response bit in the
PCI Command register, bit 6). In the 82559, the initial value of the Detected
Parity Error bit is 0b. This bit is set until cleared by writing a 1b.
This bit indicates when the device has asserted SERR#. In the 82559, the
initial value of the Signaled System Error bit is 0b. This bit is set until
cleared by writing a 1b.
This bit indicates whether or not a master abort has occurred. This bit must
be set by the master device when its transaction is terminated with a
master abort. In the 82559, the initial value of the Received Master Abort
bit is 0b. This bit is set until cleared by writing a 1b.
This bit indicates that the master has received the target abort. This bit
must be set by the master device when its transaction is terminated by a
target abort. In the 82559, the initial value of the Received Target Abort bit
is 0b. This bit is set until cleared by writing a 1b.
This bit indicates whether a transaction was terminated by a target abort.
This bit must be set by the target device when it terminates a transaction
with target abort. In the 82559, this bit is always set to 0b.
These two bits indicate the timing of DEVSEL#:
In the 82559, these bits are always set to 01b, medium.
30
00b - Fast
01b - Medium
10b - Slow
11b - Reserved
29
28
27
0 0
26
0
25
0
1
24
Description
23
1
22
0
Networking Silicon — 82559
21
0
20
1
19
Reserved
16
57
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