L64105 LSI Logic Corporation, L64105 Datasheet - Page 104

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 4.23
4-22
Reg. 72
Reg. 73
MSB
LSB
Registers 72 and 73 (0x048 and 0x049) Video ES Channel Buffer Start
Address [13:0]
7
Reserved
Video Numitems/Pics Panic Mode Select [1:0]
Reserved
Registers 70 and 71 (0x046 and 0x047)
These registers allow the host to program the Video ES channel buffer
start address. The address is entered as if it were the upper 14 bits of a
21-bit address for a conventional 2M x 16 RAM address. The Memory
Register Descriptions
6
Video ES Channel Buffer Start Address [7:0]
When INTRn is asserted, the host should read Registers
0 through 4 to determine the cause of the interrupt, take
the necessary action, and deassert INTRn by setting the
Clear Interrupt Pin bit (Register 6, bit 0,
This field allows the host to select a “panic” mode as
shown in the following table.
Bits
0b00
0b01
0b10
0b11
When enabled in either the Video Numitems Panic Mode
or the Pics-in-channel Panic Mode, the Video Decoder
suspends decoding when the number of items (64-bit
words) or the number of complete encoded and
compressed pictures in the Video ES channel buffer falls
below the Video Channel Numitems threshold value
written in Registers 134, 135, and 136
host. This helps to handle potential video channel
underflow situations gracefully without interrupting the
host. During a panic situation, the display is frozen
(freeze field) on the last picture displayed before the
panic was recognized.
5
Video ES Channel Buffer Start Address [13:8]
Description
Disable panic feature
Video numitems panic
mode
Pics-in-channel panic mode
Reserved
R/W
R/W
Reserved
(page
page
4-32) by the
4-10).
R/W [4:3]
0
[7:5]
[7:0]