L64105 LSI Logic Corporation, L64105 Datasheet - Page 123

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 4.55
Figure 4.56
7
7
Register 194 (0x0C2) Host SDRAM Read Data [7:0]
Register 195 (0x0C3) Host SDRAM Write Data [7:0]
DMA SDRAM Transfer Byte Ordering
Reserved
This register stores the next byte to be read by the host during a host
read from SDRAM.
The host writes the next byte to be read into SDRAM in this register
during a host write to SDRAM.
Memory Interface Registers
Host SDRAM Read Data [7:0]
Host SDRAM Write Data [7:0]
cycles per refresh period (1 refresh period per
macroblock during reconstruction).
Refresh
Extend
0b00
0b01
0b10
0b11
Little Endian/Big Endian
This bit must be set if the external DMA controller
operates in big endian mode, i.e., with byte 0 in bits
[63:56] and byte 7 in bits [7:0]. Since the L64105
operates in big endian mode, no byte swapping occurs at
the host interface. If the DMA controller is little endian,
this bit must be cleared to enable byte swapping.
Clear this bit when writing to this register.
Read Only
Write
Refresh Cycles
2 (default)
4
16
1 (Reserved for LSI Logic internal use only.)
0
0
4-41
6
7