L64105 LSI Logic Corporation, L64105 Datasheet - Page 378

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Table 11.7
1. Tc = 1/27 MHz = 37 ns.
11-12
Parameter
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Host Interface AC Timing (Intel Mode)
Description
Addr setup to Write / Read falling
Addr hold from Write / Read falling
CSn setup to Write / Read falling
CSn hold from Write / Read rising
Write low pulse width (Write Cycle)
Write rising to Write rising (Write Cycle)
Data setup to Write rising
Data hold from Write rising
CSn falling to WAITn / DTACKn active
Write / Read falling to WAITn low / DTACKn high
CSn rising to WAITn /DTACKn 3-state
Write falling to WAITn high / DTACKn low (Write cycle)
Write / Read rising to WAITn low / DTACKn high
Read low pulse width (Read Cycle)
Read falling to Read falling (Read Cycle)
Read falling to WAITn high / DTACKn low (Read Cycle)
Data setup BEFORE WAITn high/ DTACKn low (Read
Cycle)
Read falling to Data 3-state (Read Cycle)
Specifications
3.5 Tc
4.5 Tc
3 Tc
4 Tc
Min
10
10
7
7
7
0
0
–
–
2
–
–
–
2
1
1
1
1
2.5 Tc
3.5 Tc
Max
12
12
15
15
–
–
–
–
–
–
–
–
–
–
–
–
1
1
+ 15
+ 15
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns