L64105 LSI Logic Corporation, L64105 Datasheet - Page 113

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

Figure 4.41
Figure 4.42
Reg. 128
Reg. 129
Reg. 130
Reg. 131
Reg. 132
Reg. 133
MSB
MSB
LSB
LSB
Registers 128–130 (0x080–0x082) Picture Start Code Read Address [19:0]
Registers 131–133 (0x083–0x085) Audio Sync Code Read Address [19:0]
7
7
These registers contain the address of the video channel read pointer
captured at the time that a picture start code is decoded from the
bitstream by the decoder. When set, the most significant bit (bit 3 of
Register 130) indicates that the read pointer has wrapped around from
the end address to the start address of the buffer.
These registers contain the address of the audio channel read pointer
captured at the time that an audio sync code is decoded from the
bitstream by the Audio Decoder. When set, the most significant bit (bit 3
of Register 133) indicates that the read pointer has wrapped around from
the end address to the start address of the buffer.
Video Decoder Registers
Reserved
Reserved
Picture Start Code Read Address [15:8]
Audio Sync Code Read Address [15:8]
Picture Start Code Read Address [7:0]
Audio Sync Code Read Address [7:0]
4
4
Read Only
Read Only
Read Only
Read Only
Picture Start Code Read Address [19:16]
Audio Sync Code Read Address [19:16]
3
3
Read Only
Read Only
0
0
4-31