L64105 LSI Logic Corporation, L64105 Datasheet - Page 330

• Manufacturer Part Number: L64105
• Description: Mpeg-2 Audio/video Decoder
• Manufacturer: LSI Logic Corporation

9.12 Pulldown Operation
9-38
The 3:2 Pulldown from Bitstream bit in Register 275
to the set state at power-up or reset of the L64105. This causes the
internal microcontroller to use the top field first and repeat first field bits
in the picture coding extension of the bitstream. If both bits are set, the
microcontroller commands the Display Control Subsystem to display the
top field first in every frame and repeat it after the bottom field in
alternate frames. This displays five fields for every four in the bitstream
and is generally used to achieve frame rate conversion from
24 frames/second to 30 frames/second. Other frame rate conversions
can also be achieved.
The host can control pulldown by first clearing the 3:2 Pulldown from
Bitstream bit. This commands the microcontroller to ignore the pulldown
bits in the bitstream. The host must then toggle the Host Top Field First
and Host Repeat First Field bits in Register 275 on a frame-by-frame
basis as shown in the timing of
During 3:2 pulldown, reconstruction is stalled to avoid overwriting the
frame memory. Similar to the freeze operation, the pulldown control
signals are sampled at the frame boundary.
The First Field bit in Register 275
Register 276 can be monitored by the host to determine which field in
the frame is currently being displayed. When both bits are cleared, a
middle field is being displayed as in pulldown or freeze modes.
Video Interface
Figure
(page
9.19.
4-62) and the Last Field bit in
(page
4-62) defaults