L64105 LSI Logic Corporation, L64105 Datasheet - Page 55
L64105
Manufacturer Part Number
L64105
Description
Mpeg-2 Audio/video Decoder
Manufacturer
LSI Logic Corporation
Datasheet
1.L64105.pdf
(454 pages)
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Table 3.3
1. The channel must be stopped to access these registers. Addresses SDRAM at 256-byte boundaries.
2. SDRAM addresses at 8-byte boundaries. A 1 in the most significant bit indicates that the circular
3. SDRAM addresses at 8-byte boundaries. Bytes must be read in a least, next, and most significant
4. Cleared after read.
(Sheet 7 of 7)
(Dec)
Addr
152–
147
148
149
150
151
191
buffer has executed a “wraparound.” Bytes must be read in a least, next, and most significant order.
order.
(Hex)
Addr
98–
BF
93
94
95
96
97
Video Decoder Registers (Cont.)
Bit(s)
1:0
3:2
5:4
7:6
7:0
7:2
7:0
7:0
0
1
Summary by Register
R/W
R/W
R/W
R/W
R
R
R
R
Default
Value
(Hex)
00
0
0
0
0
0
0
0
–
–
–
Status/Command/Data
Audio PES Header Enable [1:0]
System Header Enable [1:0]
Pack Header Enable [1:0]
Reserved
Reserved
Audio Packet Error Status
Video Packet Error Status
Reserved
Pictures in Video ES Channel Buffer Counter
[7:0]
Pictures in Video ES Channel Buffer Counter
[15:8]
Reserved
4
4
Page
4-36
4-37
4-37
4-38
Ref.
3-13
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